Showing posts with label 22nm. Show all posts
Showing posts with label 22nm. Show all posts

Is Intel Really Rewriting Moore's Law With Atom?


Intel opens China fab


Intel Corp. has begun operations within its first fab in China, according to Dow Jones. In 2007, Intel won approval to build a $2.5 billion, 300-mm wafer plant in northern China for chip sets. The plan called for the fab to be in the city of Dalian. The fab will produce 65-nm devices.

Intel is also expanding in the U.S. As reported, Intel recently confirmed speculation that it will build a new R&D wafer fab in Hillsboro, Ore., and upgrade other existing U.S. facilities for 22-nm production at a total investment of between $6 billion and $8 billion.

The investment will create 800 to 1,000 permanent high-tech jobs and 6,000 to 8,000 construction jobs, Intel (Santa Clara, Calif.) said. The new development fab in Oregon, to be known as D1X, is slated for R&D startup in 2013.

One analyst thinks the fab will be ''450-mm ready.'' [Via: EETimes]

GlobalFoundries tech park in trouble?


A New York state agency plans to take over a technology park that houses the new 300-mm fab owned by U.S. silicon foundry upstart GlobalFoundries Inc.

GlobalFoundries' wafer fab under construction in New York state, Fab 8, would run the 22-nm production and more advanced nodes. Construction for Fab 8 started in July of 2009. The fab will have 60,000 wafer starts per month once it goes into full production. Production is expected to go online in 2012.

''The Fab 8 project is on schedule and construction is progressing very smoothly. We just have some concerns about a few pieces of infrastructure that need to be delivered. The state and (Luther Forest) are working out the details and we are confident they will address our concerns,'' according to a spokesman for GlobalFoundries.[Via: EETimes]

Restrictive Design Rules and Their Impact on 22nm Design and Physical Verification


Process variability is posing considerable challenge to the capability of lithography and manufacturing techniques, and thus impacts both performance and yield of advanced node chips. To ensure the manufacturability and performance of chips at 22nm, one approach the industry is considering is restrictive design&mash;limiting the type and placement of features used in designs. Gridding of critical layers significantly reduces the total physical design space available and makes restrictive design possible. This paper examines the basics of gridding, the requirements for restrictive gridded design, and the automated methods for accurate checking of Restrictive Design Rules (RDRs). Resolving the debug challenges associated with the implementation of checking restrictive design and grid rules is also discussed.