Transport delay / Inertial Delay / Delta Delay

In Verilog and VHDL, there are three types of delays that are commonly used in digital logic simulation: delta delay, transport delay, and inertial delay. 

Here are the differences between the three types of delays along with code examples in both Verilog and VHDL:

Delta Delay:

Delta delay is a zero-delay delay model that is used to model events that occur in the current simulation time. Delta delay is also referred to as zero-time delay or simulation delay.

In Verilog, delta delay is implicit and does not require any special syntax. 

In VHDL, delta delay is explicitly modeled using the keyword "delta".

Here's an example of using delta delay in Verilog:

always @(posedge clk) begin

    if (enable) begin

        data_out <= data_in;

    end

end

Here's an example of using delta delay in VHDL:

process(clk)

begin

    if rising_edge(clk) then

        if enable = '1' then

            data_out <= data_in;

        end if;

    end if;

end process;

Transport Delay:

Transport delay is a delay model that represents the time it takes for a signal to propagate through a gate or a wire. Transport delay is also referred to as unit delay.

In Verilog, transport delay is explicitly modeled using the keyword "#". In VHDL, transport delay is modeled using the keyword "after".

Here's an example of using transport delay in Verilog:

always @(posedge clk) begin

    if (enable) begin

        #1 data_out <= data_in;

    end

end

Here's an example of using transport delay in VHDL:

process(clk)

begin

    if rising_edge(clk) then

        if enable = '1' then

            data_out <= data_in after 1 ns;

        end if;

    end if;

end process;

Inertial Delay:

Inertial delay is a delay model that represents the time it takes for a signal to propagate through a gate or a wire, but with a minimum duration that must be met before the signal is propagated. Inertial delay is also referred to as realistic delay or event delay.

In Verilog, inertial delay is modeled using the "##" operator. In VHDL, inertial delay is modeled using the keyword "inertial".

Here's an example of using inertial delay in Verilog:

always @(posedge clk) begin

    if (enable) begin

        if (data_in ##1 ns) begin

            data_out <= data_in;

        end

    end

end

Here's an example of using inertial delay in VHDL:

process(clk)

begin

    if rising_edge(clk) then

        if enable = '1' then

            if data_in'event and data_in = '1' after 1 ns then

                data_out <= data_in;

            end if;

        end if;

    end if;

end process;

The main differences between delta delay, transport delay, and inertial delay are the way they model delay in digital logic simulation. 

1. Delta delay is a zero-delay model
2. Transport delay represents the delay through a gate or a wire
3. Inertial delay represents realistic delay with a minimum duration that must be met.

Please leave a comment if you have any further questions!