"Latch" Vs "Flip Flop"

A flip-flop is Edge sensitive: Output only changes on rising (or falling) edge of clock.
A latch is Level sensitive: Output changes whenever clock/Enable is high (or low)

A common implementation of a flip-flop is a pair of latches (Master/Slave flop).

Latches are sometimes called “transparent latches”, because they are transparent (input directly connected to output) when the clock is high.

The clock to a latch is primarily called the “enable”.

For more information have a look at the picture below.







Deprecated Hardware:

Latches:
  1. Use flops, not latches
  2.  Latch-based designs are susceptible to timing problems
  3. The transparent phase of a latch can let a signal “leak” through a latch — causing the signal to affect the output one clock cycle too early
  4. It’s possible for a latch-based circuit to simulate correctly, but not work in real hardware, because the timing delays on the real hardware don’t match those predicted in synthesis
Flip-flops:
  1. Limit yourself to D-type flip-flops
  2. Some FPGA and ASIC cell libraries include only D-type flip flops. Others, such as Altera’s APEX FPGAs, can be configured as D, T, JK, or SR flip-flops.
  • For every signal in your design, know whether it should be a flip-flop or combinational. Examine the log file e.g. dc shell.log to see if the flip-flops in your circuit match your expectations, and to check that you don’t have any latches in your design.
  • Do not assign a signal to itself (e.g. a <= a; is bad). If the signal is a flop, use an enable to cause the signal to hold its value. If the signal is combinational, then assigning a signal to itself will cause combinational loops, which are very bad.
If you are looking for code snippets for the following types of hardware, please leave a comment.
  1. Flops with Waits and Ifs
  2. Flops with Synchronous Reset
  3. Flops with Chip-Enable
  4. Flops with Chip-Enable and Mux on Input
  5. Flops with Chip-Enable, Mux's, and Reset

19/Post a Comment/Comments

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  1. Thanx,
    A latch is a level-triggered device and a flipflop is an edge-triggered device.

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  2. this just really helped me out thank you!!

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  3. Quite a important concept , I got screwed for my first interview when i said that both were the same ( i had forgotten ), its not going to happen again

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  4. Yes you are right! It's important to call things with it's names...

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  5. thanks. This is a very good clarification. saying that a flip-flop is edge sensitive and latch is level sensitive is not a good enough definition. It must be made clear that when a latch is enabled it becomes transparent while a flip flop's output only changes on the clock edge.

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  6. thanks for the valuable knowledge

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  7. There are different ways to answer this question..
    a) A M/S F/F is made of two latches called phi2 and phi1
    b) a latch is created from a keeper element fed by a passgate.. the pass gate opens when the enable is clocked .
    c) The latch and a edge triggered F/F also have different setup edges..

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  8. can ayone tell me why reset is always kept low in cmos logic ckts?

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  9. can nyone tell me why reset is always kept low in cmos logic ckts

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  10. whats the design diff for different clk pulse based activation i.e. level or edge?

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  11. thanks, we explained and good advice! Best wishes from Finland!

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  12. Great post! Readers might also enjoy Steve Mackay’s engineering blog at http://www.idc-online.com/Engineering-Blog and the free technical resources available there.

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  13. This comment has been removed by a blog administrator.

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