Showing posts with label 32nm. Show all posts
Showing posts with label 32nm. Show all posts

Is Intel Really Rewriting Moore's Law With Atom?


Challenges for the 28nm half node: Is the optical shrink dead?


A half-node process has been routinely used to deliver incremental improvements in process control and hardware availability in order to continue Moore's Law. Traditionally, due to the imaging requirements, parameters such as numerical aperture and partial coherence were not set to their maximum resolution settings, thus leaving room in hardware and RET recipes to accommodate incremental imaging requirements. However, as hardware availability and computational lithography methods are stressed to the maximum of their capabilities to deliver the next technology nodes, it is worth asking the question if such optical shrinks continue to be viable moving forward. Already 28nm layouts scaled down from the original 32nm layouts are starting to show signs of configuration limitations dictated by the available imaging hardware. In this paper its is shown that two-dimensional features determine the feasibility of migrating successfully to the next half-node even when one-dimensional metrics suggest that such migration should be possible.