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Clock meshes are used in state-of-the-art designs to construct clock routing in contrast to clock trees in older design. This shift in clock tree construction methodology is motivated by the fact that meshes cope better with variability effects. How do you use SPICE simulations to measure the skew of tree routing versus grid clock routing while taking variability effects into consideration. Can you extend your study to non-tree routings, i.e., clock trees with added short cuts? Also can you include delay comparison between tree and non-tree structures?