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Clock meshes are used in state-of-the-art designs to construct clock routing in contrast to clock trees in older design. This shift in clock tree construction methodology is motivated by the fact that meshes cope better with variability effects. How do you use SPICE simulations to measure the skew of tree routing versus grid clock routing while taking variability effects into consideration. Can you extend your study to non-tree routings, i.e., clock trees with added short cuts? Also can you include delay comparison between tree and non-tree structures?
Clock skew is a function of process variation, i.e., delay from the clock source to a leave of the clock tree is a statistical function. A rule of thumb for minimum process variation clock tree design is to have balanced branches, i.e., identical buffers from identical distances to the clock source, and symmetric clock routing branches with identical capacitive loads. Can you have a more flexible clock tree design scheme, while maintaining a minimized/bounded clock skew from a statistical point of view?
Re-timing reduces longest combinational logic paths by relocating some of the flip-flops, both logically and physically. How do you evaluate the effectiveness of re-timing, with existing tools and/or some of your own scripts? Comparing with useful clock skew is a plus.