Showing posts with label Coding. Show all posts
Showing posts with label Coding. Show all posts

Simple XVGA (1024x768) Controller in Verilog


module xvga(clk,hcount,vcount,hsync,vsync);
input clk; // 64.8 Mhz
output [10:0] hcount;
output [9:0] vcount;
output hsync, vsync;
output [2:0] rgb;

reg hsync,vsync,hblank,vblank,blank;
reg [10:0] hcount; // pixel number on current line
reg [9:0] vcount; // line number

wire hsyncon,hsyncoff,hreset,hblankon; // next slide for generation
wire vsyncon,vsyncoff,vreset,vblankon; // of timing signals
wire next_hb = hreset ? 0 : hblankon ? 1 : hblank; // sync & blank
wire next_vb = vreset ? 0 : vblankon ? 1 : vblank;

always @(posedge clk) begin
hcount <= hreset ? 0 : hcount + 1;
hblank <= next_hb;
hsync <= hsyncon ? 0 : hsyncoff ? 1 : hsync; // active low
vcount <= hreset ? (vreset ? 0 : vcount + 1) : vcount;
vblank <= next_vb;
vsync <= vsyncon ? 0 : vsyncoff ? 1 : vsync; // active low
end

// assume 65 Mhz pixel clock
// horizontal: 1344 pixels total
// display 1024 pixels per line
assign hblankon = (hcount == 1023); // turn on blanking
assign hsyncon = (hcount == 1047); // turn on sync pulse
assign hsyncoff = (hcount == 1183); // turn off sync pulse
assign hreset = (hcount == 1343); // end of line (reset counter)
// vertical: 806 lines total
// display 768 lines
assign vblankon = hreset & (vcount == 767); // turn on blanking
assign vsyncon = hreset & (vcount == 776); // turn on sync pulse
assign vsyncoff = hreset & (vcount == 782); // turn off sync pulse
assign vreset = hreset & (vcount == 805); // end of frame

// for frame
always @(posedge clk) begin
if (vblank | (hblank & ~hreset)) rgb <= 0;
else
rgb <= (hcount==0 | hcount==639 | vcount==0 | vcount==479) ? 7 : 0;
end

//for colors (see below)
always @(posedge clk) begin
if (vblank | (hblank & ~hreset)) rgb <= 0;
else
rgb <= hcount[8:6];
end

Color chart:

RGB Color

000 black
001 blue
010 green
011 cyan
100 red
101 magenta
110 yellow
111 white


Example Pixel:


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“behavioural model” & “structural model”


The phrases "behavioural model" and "structural model" are commonly used for what we'll call "high-level models" and "synthesizable models". In most cases, what people call structural code contains both structural and behavioural code. The technically correct definition of a structural model is an HDL program that contains only component instantiations and generate statements. Thus, even a program with c <= a AND b; is, strictly speaking, behavioural.

Verilog code to detect if a 64bit pattern can be expressed using power of 2


module pat_det ( data_in, patDetected );

input [31:0] data_in;
output patDetected;

wire [4:0] patSum = data_in[0] + data_in[1] + data_in[2] +
data_in[3] + data_in[4] + data_in[5] +
data_in[6] + data_in[7] + data_in[8] +
data_in[9] + data_in[10] + data_in[11] +
data_in[12] + data_in[13] + data_in[14] +
data_in[15] + data_in[16] + data_in[17] +
data_in[18] + data_in[19] + data_in[20] +
data_in[20] + data_in[21] + data_in[22] +
data_in[23] + data_in[24] + data_in[25] +
data_in[26] + data_in[27] + data_in[28] +
data_in[29] + data_in[30] + data_in[31] ;

wire patDetected = (patSum == 1)? 1'b1: 1'b0;

endmodule

Verilog Shift Register with Test Bench


module shifter (result, value_in, direction, type, length);
output [7:0] result;
input [7:0] value_in;
input direction;
input [1:0] type;
input [2:0] length;

reg [7:0] value_out;

always @(value_in or direction or type or length)
begin
case ({direction, type})
3'b0_00: value_out = value_in >> length;
3'b0_01: case(length)
3'b000: value_out = value_in;
3'b001: value_out = {value_in[7], value_in[7:1]};
3'b010: value_out = {{2{value_in[7]}}, value_in[7:2]};
3'b011: value_out = {{3{value_in[7]}}, value_in[7:3]};
3'b100: value_out = {{4{value_in[7]}}, value_in[7:4]};
3'b101: value_out = {{5{value_in[7]}}, value_in[7:5]};
3'b110: value_out = {{6{value_in[7]}}, value_in[7:6]};
3'b111: value_out = {{7{value_in[7]}}, value_in[7]};
endcase
3'b0_10: case(length)
3'b000: value_out = value_in;
3'b001: value_out = {value_in[0], value_in[7:1]};
3'b010: value_out = {value_in[1:0], value_in[7:2]};
3'b011: value_out = {value_in[2:0], value_in[7:3]};
3'b100: value_out = {value_in[3:0], value_in[7:4]};
3'b101: value_out = {value_in[4:0], value_in[7:5]};
3'b110: value_out = {value_in[5:0], value_in[7:6]};
3'b111: value_out = {value_in[6:0], value_in[7]};
endcase
3'b1_00: value_out = value_in << length;
3'b1_01: value_out = {value_in[7], value_in[6:0] << length};
3'b1_10: case(length)
3'b000: value_out = value_in;
3'b001: value_out = {value_in[6:0], value_in[7]};
3'b010: value_out = {value_in[5:0], value_in[7:6]};
3'b011: value_out = {value_in[4:0], value_in[7:5]};
3'b100: value_out = {value_in[3:0], value_in[7:4]};
3'b101: value_out = {value_in[2:0], value_in[7:3]};
3'b110: value_out = {value_in[1:0], value_in[7:2]};
3'b111: value_out = {value_in[0], value_in[7:1]};
endcase
default: value_out = value_in;
endcase
end
assign result = value_out;
endmodule

--


module testbench;

reg clk, direction;
reg [1:0] type;
reg [2:0] length;
reg [7:0] value_in;

wire [7:0] result;

shifter shifter1(result, value_in, direction, type, length);

initial
begin
clk = 0;
direction = 1;
type = 1;
length = 3;
value_in = 'b11110110;

$display("direction = %d type = %d length = %d value_in = %b", direction, type, length, value_in);

#10 $display("done");

$finish;
end

always #5 clk = !clk;
always @(posedge clk)
$strobe("result: %b", result);
endmodule

Verilog Awareness


Differentiate between Inter assignment Delay and Inertial Delay ?

What are the different State machine Styles ? Which is better ? Why and when do we use one ove the other? Explain Disadv. and Adv.?

What is the difference between the following lines of code ?
  1. reg1<= #10 reg2 ;
  2. reg3 = # 10 reg 4 ;
What is value of Var1 after the following assignment ?
  1. reg Var1;
  2. initial begin
  3. Var1<= "-"
  4. end
What is the output of the below code?
  1. module quest_for_out();
  2. integer i;
  3. reg clk;
  4. initial begin
  5. clk = 0;
  6. #4 $finish;
  7. end
  8. always #1 clk = !clk;
  9. always @ (posedge clk)
  10. begin : FOR_OUT
  11. for (i=0; i < 8; i = i + 1) begin
  12. if (i == 5) begin
  13. disable FOR_OUT;
  14. end
  15. $display ( "Current i : %g" ,i);
  16. end
  17. end
  18. endmodule

What is the output of the below code?

  1. module quest_for_in();
  2. integer i;
  3. reg clk;
  4. initial begin
  5. clk = 0;
  6. #4 $finish;
  7. end
  8. always #1 clk = !clk;
  9. always @ (posedge clk)
  10. begin
  11. for (i=0; i < 8; i = i + 1) begin : FOR_IN
  12. if (i == 5) begin
  13. disable FOR_IN;
  14. end
  15. $display ( "Current i : %g" ,i);
  16. end
  17. end
  18. endmodule

Verilog Awareness


  • Consider a 2:1 mux , what will be the output F if the Select (sel) is "X" ?
  • What is the difference between blocking and nonblocking assignment? Explain with a simple example?
  • What is the difference between wire and a reg data type?
  • Write code for async reset D-Flip-Flop, Shift Register.
  • Write code for 2:1 MUX using different coding styles.
  • Write code for parallel encoder and priority encoder.
  • Different "case" usage styles! Explain.
  • What is the difference between === and == ?
  • Why is defparam used for ?
  • What is the difference between unary operator and logical operator ?
  • What is the difference between task and function ?
  • What is the difference between transport and inertial delays?
  • What is the difference between casex and case statements ?
  • What is the difference between $monitor and $display ?
  • What is the difference between compiled, interpreted, event based and cycle based simulator ?

Verilog Blocking Vs Non Blocking, Myths and Facts


I know people who swear by blocking and some who swear by non-blocking.

So here are some thoughts.
There is very little difference between non-blocking and blocking in speed and no errors if done correctly either way.

The main differences are:
Some people like non-blocking because you can tell that a reg on the left hand side of <= is going to be a flip flop after synthesis.

/* example 1a */
reg a,b,c;
always @(posedge clock)
begin b <= a;
/* b and c will be flip flops */
c <= b;
end

/* example 1b */
reg a,b,c;
always @(posedge clock)
begin
c <= b;
b <= a;
/* b and c will be flip flops */
end

/* example 2a */
reg a,b,c;
always @(posedge clock)
begin
b = a;
c = b;
/* Only c will be a flip flop,b will go away after synthesis. */
/* We could delete the 2 above assignments and replace it with c=a;b=a; In fact, b is the same as c and can be eliminated.*/
end

/* example 2b */
reg a,b,c;
always @(posedge clock)
begin
c = b;
b = a;
/* Both b and c will be flip flops, because these 2 lines are reversed.*/
end

Example 1a, 1b and 2b are functionally the same.
Example 2a is functionally different from 2b just because the order of the statements.

Some people like blocking because it takes less memory in the simulator.

/* example NON-BLOCKING_MEMORY */
reg a,b,c;
always @(posedge clock)
begin
/* b will require 2 memory locations*/
b <= a;
/*<---because this b memory location will hold value of a */
c <= b;
/*<---and this b memory location will hold value of b before the posedge*/
end

/* example BLOCKING_MEMORY */
reg a,b,c;
always @(posedge clock)
begin
// b will require ONLY 1 memory location
c = b;
b = a;
end

Note that I am talking about SIMULATOR memory, not flip-flop count after synthesis. In most cases, the simulator has to remember the value before and after posedge clock if a reg goes between modules in order in order to "execute modules in parallel", so there may be no savings.

Some people like blocking because you can see sharing of resources more readily.
// example 5

reg [15:0] a,b,c,d,e,f,j,k,g,h;
reg [16:0] x,y,z;
always @(posedge clock)
begin
x = a + b + c + d + e + f + j + k;
y = x + g;
z = x + h;
end

// example 6
reg [15:0] a,b,c,d,e,f,j,k,g,h;
reg [16:0] y,z;
always @(posedge clock)
begin
y <= (a + b + c + d + e + f + j + k) + g;
z <= (a + b + c + d + e + f + j + k) + h;
end

Even the cheapest synthesizer should share adder logic in example 5, but a slightly smarter synthesizer is required in example 6.

You will have fewer problems with race conditions in SIMULATION if you always use non-blocking assignments inside always @(posedge clock) blocks where you want to have flip-flops.

file xyz.v :
module xyz(a,b,clk);
input b,clk;
output a;
reg a;
always @(posedge clk)
a = b;
endmodule

file abc.v :
module abc(b,c,clk);
input c, clk;
output b;
reg b;
always @(posedge clk)
b = c;
endmodule

Some of the simulators out there will execute module abc first and then module xyx.
This effectively transfers contents of c to a in ONE clk cycle. This is what some people refer to as a simulator race conditon. Other simulators will execute module xyz and then module abc giving a different simulation result. In some simulators, order of execution cannot be controlled by users.

Design Guidelines and Criteria for Digital Electronics


..apparently these pages on guidelines and criteria, are from NASA. I think this is a very nice article with good amount discussion on critical aspects of Digital Design.

http://klabs.org/DEI/References/design_guidelines/nasa_guidelines/clocks/clocks.htm