Showing posts with label Cycle Simulation. Show all posts
Showing posts with label Cycle Simulation. Show all posts

Cycle based simulation

New design starts continue to grow in gate count, and the amount of CPU time required to simulate these designs tends to grow disproportionate to gate count, implying a growing need for simulation speed. A simple example helps to shed light
on this situation.
Suppose a circuit has n functions and that, in the worst case, each function interacts with all of the others. Ignoring for the moment the complexity of the interactions, there are n × (n − 1)/2 potential interactions between the n functions.

Thus, in the worst case, the number of interactions grows proportional to the square of the number of functions. Handshaking protocols between functions also grow more complex. Internal status and mode control registers act as extensions to device I/O pins.

To verify the growing number of interactions requires more stimuli. In addition, the growing number of gates and functions in the circuit model generate more events that must be evaluated during each clock cycle. The combination of more functionality and more stimuli requires an exponentially growing amount of CPU time to complete the evaluations. A consequence of this is a growing difficulty to create and simulate enough stimuli to verify design correctness. As a result, design errors are more likely to escape detection until after tape-out, at which time the discovery of errors requires another expensive iteration through the design cycle.

Cycle simulation is one of the answers to the growing need for greater verification power. Cycle simulation evaluates logic elements and functions across clock cycle boundaries without regard to intermediate values. Its purpose is to evaluate input stimuli as rapidly as possible. Designs are required to be synchronous so that every possible technique can be leveraged during simulation. Rank-ordering is used so that elements only need to be evaluated once during each clock period. Circuit delays are ignored, and the number of logic values is usually limited to three or four {0, 1, X, Z}. Internal representation of the circuit may be in terms of binary decision diagrams (BDDs), so intermediate values are totally obscured. To insure that a circuit operates at its intended speed when fabricated, circuit delays are measured by timing analysis programs that are written specifically for that purpose and run independently of simulation.

The designer plays a role in this simulation mode by modeling circuits at the highest possible level of abstraction without losing essential details. A number of methods have been developed to speed up simulation while reducing the amount of workstation memory required to perform simulations.

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