Showing posts with label DDR2. Show all posts
Showing posts with label DDR2. Show all posts

Dealing with clock jitter in DDR2/DDR3 based designs


For the past couple of days i have been part of a design that interfaces a DDR/DDR2 memory. But lately after a recent pll model integration the whole scenario changed and i was in the middle of a clock jitter related timing check failure. This led me to do some Google search when i found this interesting 3 part article based on the same title.

Defining clock jitter
DDR2/DDR3 functionality
Clock jitter and statistics