Test
What is IJTAG: A Standard for Accessing Embedded Instruments
Introduction If you are a chip designer or a test engineer, you may have heard of JTAG, a standard that provides a way …
DFT
Technology
Stuck-at-Fault Model (SAF) and Transition-Delay-Fault Model (TDF) Charatcteristics and Application
In the context of silicon design for test (DFT), there are several techniques and methodologies that are used to improv…
Testing
At-Speed and Advanced Fault Models for Achieving High Quality Test
With the increasing clock speeds and the decreasing feature sizes found in today's nanometer designs, at-speed tes…
Testing
The Economics of Test, Part - IV
Detecting a defective unit is often only part of the job. Another important aspect of test economics that must be consi…
Testing
The Economics of Test, Part - III
However, if devices are tested, feature sizes can be reduced and more die will fit on each wafer. Even after the die ar…
I have something to explain
The Economics of Test, Part - II
The table depicted shows test cost broken down into four categories some of which are one-time, non recurring costs whe…
I have something to explain
The Economics of Test, Part - I
What are the factors that influence the cost of test? Quality and test costs are related, but they are not inverse of o…
Formal Verification
When are DFT and Formal verification used?
DFT: manufacturing defects like stuck at "0" or "1". test for set of rules followed during the init…
Verification
Application Specific Integrated Circuit ( ASIC )
An application-specific integrated circuit or ASIC comprises an integrated circuit (IC) with functionality customized f…