Showing posts with label Events. Show all posts
Showing posts with label Events. Show all posts

Upcoming VLSI/IC Conference - Cool Chips 2009


Cool Chips 2009
IEEE Symposium on Low-Power and High Speed Chips
Yokohama, Japan
April 15-17, 2009

COOL Chips is an International Symposium initiated in 1998 to present advancement of low-power and high-speed chips. The symposium covers leading-edge technologies in all areas of microprocessors and their applications. The COOL Chips XII is to be held in Yokohama on April 15-17, 2009, and is targeted at the architecture, design and implementation of chips with special emphasis on the areas listed below. The COOL Chips Organizing Committee will ask the MICRO to publish selected papers in a special issue on COOL Chips XII.

Contributions are solicited in the following areas:

* Low Power-High Performance Processors for Multimedia, Digital Consumer Electronics, Mobile, Graphics, Encryption, Robotics, Networking and Biometrics.
* Novel Architectures and Schemes for Single Core, Multi-Core, Embedded System, Reconfigurable Computing, Grid, Ubiquitous, Dependable Computing and Wireless.
* Cool Software including Binary Translations, Compiler Issues and Low Power Techniques.

List of VLSI & IC Conferences and Workshops


CoWare upcoming webinars!


CoWare the leading global supplier of platform-driven electronic system-level (ESL) design software and services is arranging a series of online Webinars based on Processor Design, Software Development and Wireless Design to benefit the user. The webinars will be held on the following dates:

Wednesday, 18th March:
Custom Processor / Programmable Accelerator Design and Implementation.

Tuesday, 31st March:
Getting Started with Virtual Platforms: A Software Developer Perspective.

Wednesday, 8th April:
Challenges for LTE Wireless Systems Design.

These webinars will also be recorded for viewing it later as per participant’s convenience.

Here are the details of the Webinars with the registration link:
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Wednesday, March 18, 2009
9 am Pacific (9:30 PM IST)
Length: 1 hour
Presenter: Drew Taussig

Custom Processor / Programmable Accelerator Design and Implementation
As companies are looking to improve their competitive advantage, the need for programmable hardware accelerators, ASIPs and custom processors is growing rapidly. They provide the solution to performance and flexibility challenges electronic system designers are facing today. But, in today s economy where there are fewer resources and everyone has cost reduction on their mind, how can you design them efficiently? How can you generate efficient RTL? How can you equip the software developers with the right linker, assembler, compiler, simulator and debugger?

What you will learn:
* Concepts and reasons behind developing custom processors and hardware programmable accelerators.
* Design and implementation steps and how these steps can be streamlined using efficient and powerful design tools that automate the exploration, RTL implementation and software development tools.
* How the generated processor can be used for development and verification in a Virtual Platform for Software Development, an FPGA or an RTL emulation environment.

Register now!

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Tuesday, March 31, 2009
9 am Pacific (9:30 PM IST)
Length: 1 hour
Presenter: Achim Nohl

Getting Started with Virtual Platforms: A Software Developer Perspective
The ability to debug and analyze software defects efficiently is a key requirement in order to complete a software project successfully and on time. Especially when porting legacy software such as an OS or migrating sequential code to multi-core platforms, powerful debugging tools and methods are indispensable. This one hour webinar gives a technical overview and various practical examples on the usage of virtual platforms for debugging. Virtual platforms enable a whole new world of software analysis and debugging solutions. An OS-aware software analysis framework eases the understanding of the history and interaction between multiple parallel software stacks. The controllability and visibility of virtual platforms enables engineers to trigger and analyze multi-processing defects such as dead-locks and race conditions. Correctness and performance of complex shared-memory communication, task scheduling and control can be asserted which results in a significant quality and productivity gain for the software engineer.

What you will learn:
* Overview of the debugging infrastructure provided by a virtual platform
* Practical examples for applying virtual platforms for embedded software debugging based on real world software and hardware configurations
* How the OS-aware analysis and debug framework can be used and customized to debug typical problems that appear during OS porting
* How domain integration problems in an asymmetric, multi-processing platform can be identified
* How virtual platforms can be used to debug shared memory communication problems based on a multi-core video driver
* How virtual platforms can be used to spot an existing bug in the Linux kernel for the ARM11 MPcore configuration

Register now!

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Wednesday, April 8, 2009
9 am Pacific (9:30 PM IST)
Length: 1 hour
Presenter: Dr. Johannes Stahl

Challenges for LTE Wireless Systems Design
Long-Term Evolution (LTE) wireless systems have 5-10x higher processing complexity than currently-deployed 3G wireless systems. This creates a unique pressure across all aspects of the handsets, the basestation and the network. Previous product platforms have to be significantly re-architected and entirely new software applications have to be developed to take advantage of the much higher bandwidth that LTE is targeted to provide. In this webinar, we will explain those design challenges and offer different approaches that design teams can take to deliver advanced products. The webinar targets development managers across the supply chain that are developing LTE products today or are planning to get involved in the near future. Whether you are a manager inside a network operator, basestation or handset OEM or you are in a semiconductor company, you should participate and learn about how you can meet your LTE product roll-out schedule within your tight development budgets.

What you will learn:
* How network operators can leverage the LTE standard to optimize their network throughput
* How chip architects will extract maximum application performance from their architectures
* How programmability of signal processing accelerators does not come at the expense of too much power
* How application or baseband processing software is developed if it is spread across multiple processor cores

Register now!