Showing posts with label Flash Memories. Show all posts
Showing posts with label Flash Memories. Show all posts

Flash Memories - Types


Although all flash memories use the same basic storage cell, there are a number of ways in which the cells can be interconnected within the overall memory array. The two most prominent architectures are known as NOR and NAND; these terms, derived from traditional combinatorial logic, indicate the topology of the array and the manner in which individual cells are accessed for reading and writing. Initially, there was a basic distinction between these two fundamentally different architectures, with NOR devices exhibiting inherently faster read times and NAND devices offering higher storage densities (because the NAND cell is about 40% smaller than the NOR cell). NOR Flash memories are considered to be the best choice for densities up to 256 Mbits, while NAND types are preferred for 512-Mbits and up. This is the best compromise between large data storage capacities and cell size - and consequently, final die size.

NOR Flash Memory:
NOR-type Flash memories are based on technologies that evolved largely from the first non-volatile memory technologies. They are typically organized as a number of blocks between 16 Kbytes and 128 Kbytes, each of which can be individually erased or programmed. The architecture can be either uniform if all of the blocks are the same size or asymmetrical when the blocks vary in size. The array can be organized as a single piece of memory or split into dual or multiple banks, and in some cases, one block (called boot block) located at the top or the bottom of the address space, is dedicated to the storage of the boot code. NOR Flash memories usually have a random access for reading at byte/word level and sometimes a page access mode, allowing the reader to view an entire page of 2 to 4 words in one go. When very rapid read operations are required, the Flash memory is equipped with a burst read mode, which allows data to be transferred on every clock cycle.

Parallel and Serial Interface:
Parallel Access and Serial Access Parallel buses were primarily used to interface flash memories with microcontrollers and microprocessors through an address bus, a data bus and a control bus. By default, the term "Flash memory" refers to a parallel interface memory. The data bus can be organized as x8 bits, x16 bits or x32 bits. In some cases, address and data buses can be multiplexed. They are available in densities of up to 128 Mbits. Because of their rapid read times, Flash memories are traditionally used for basic code or code-plus-parameter storage where greater flexibility compared to EPROM is more important than the additional unit cost. More recently, they have pervaded many new applications where their key functions are to store both code and data. This was achieved by dual operations supported by dual or multiple bank architecture, which enable programming/erasing operations in one bank while reading from another bank. The serial bus is used to connect a Flash memory to a microcontroller or an ASIC equipped with a serial bus. Serial buses are input/output interfaces supporting a mixed address/data protocol. The serial bus connectivity reduces the number of interface signals required. For example, the SPI bus, the most popular serial bus for serial Flash memories, requires only 4 signals (data in, data out, clock and chip select) compared to 21 signals necessary to interface a 10-bit address parallel memory. As a result, the number of pins of the memory package (memory and bus master) is reduced, as is the number of PCB tracks. Consequently, a serial memory can fit into a smaller and less expensive package. However, serial Flash memories are available in lower densities than Flash memories. The communication throughput between serial Flash memory and master processor is lower than for traditional Flash memories. Consequently, the time to download code into the serial memory and execute it from the memory is longer. As a result, serial Flash memories are usually used for small code storage associated with a cache RAM. This is called a code shadowing architecture. The executable code is first programmed in the memory and it is write protected. After power-up, it is downloaded from memory to RAM from where it is executed by the master processor.

Flash Memories - Introduction


Flash memory is a type of electronic memory increasingly used in a wide range of communications, consumer, computer and peripherals, and automotive applications, but which relatively few semiconductor companies can produce in volume at the low cost equipment manufacturers require. Flash memories belongs to the class of semiconductor memories called non-volatile memories, of which it is the most dynamic driving force. Semiconductor memories can be divided into two different types: those that can only retain data stored in them while they are connected to a battery or some other source of electrical power (volatile), and those that retain their data even if their power supply is removed (non-volatile).

Flash memories can be electrically erased and it is not necessary to erase the whole memory array in order to store new data in part of it. Flash memory, EPROM and EEPROM devices all use the same basic floating gate mechanism to store data, but they use different techniques for reading and writing data.

In each case, the basic memory cell consists of a single MOS transistor (MOSFET) with two gates:
• control gate connected to the read/write control circuitry
• floating gate located between the control gate and the channel of the MOSFET(the part of the MOSFET through which electrons flow between the so-called
Source and Drain terminals).

In a standard MOSFET, a single Gate terminal controls the electrical resistance of the channel: electrical voltage applied to the gate controls how much current can flow between the Source and Drain. The MOSFETs used in non-volatile memories include a second gate that is completely surrounded by an insulating layer of silicon dioxide, i.e., it is electrically isolated from the rest of the circuitry. Because the floating gate is physically very close to the MOSFET channel, even a small electric charge has an easily detectable effect on the electrical behavior of the transistor. By applying appropriate signals to the control gate and measuring the change in transistor behavior, it is possible to determine whether there is an electrical charge on the floating gate. Because the floating gate is electrically isolated from the rest of the transistor, special techniques are required to move electrons to and from the floating gate.

One method is to fill the MOSFET channel with high-energy electrons by making a relatively high current pass between the drain and the source of the MOSFET. Some of these "hot" electrons have sufficient energy to cross the potential barrier between the channels and reach the floating gate. When the high current in the channel is removed, these electrons remain trapped in the floating gate. This is the method used to program the memory cells in EPROM and Flash memories. This technique, known as Channel Hot Electron (CHE) injection, can be used to load an electrical charge onto the floating gate, but does not provide a way to discharge it. EPROM technology achieves this by flooding the entire memory array with ultra-violet light; the high-energy light rays penetrate the chip structure and impart enough energy to the trapped electrons to allow them to escape from the floating gate.

The second method of moving a charge to a floating gate is the quantum mechanical effect known as tunneling. In this method electrons are removed from the floating gate by applying a voltage that is large enough to cause electrons to 'tunnel' across the insulating oxide layer to the source between the MOSFET control gate and the source or the drain. The number of electrons that can tunnel across an insulating layer in a given time depends on the thickness of the layer and the value of the applied voltage. To meet realistic voltage levels and erase-time constraints, the insulating layer must be very thin, typically 7nm (70 Angstroms).

EEPROM memories use tunneling to charge and discharge the floating gate according to the polarity of the applied tunneling voltage. A Flash memory can therefore be considered to be a memory device that is programmed like an EPROM and erased like an EEPROM, although there is much more to Flash technology than simply grafting the EEPROM erase mechanism onto EPROM technology.

The most important difference between EPROM and the other two processes lies in the thickness of the oxide layer that separates the floating gate from the source. In an EPROM, this is typically 20-25nm, but this is far too thick to allow tunneling to take place at an acceptable rate with a practical voltage level. For Flash memory, tunnel oxide thickness of around 10nm is required, and the quality of this oxide layer has a dramatic effect on the performance and reliability of the device. This is one of the reasons that relatively few semiconductor manufacturers have mastered Flash technology and even fewer have been able to reliably combine Flash technology and mainstream CMOS processes to build products such as microcontrollers with embedded Flash memory.

In the next post on this series, we will look at NAND, NOR, Parallel & Serial Flashes!