I agree with this explanation. The thing you MUST remember when coding any RTL for synthesis is that you are designing logic, not running software on a processor. Way to often I see individuals treating RTL like it is serially executed code running on a processor. This type of code usually results in very poor synthesis and timing results. When I am given code like this to work on, usually after someone has designed something poorly, it usually gets thrown in the trash and redesigned. So, even though a software like construct exists in RTL and it "may" be synthesizable and simulate the desired function, that does not mean one should use it.
When coding RTL, you should really think about what you are trying to design in hardware, not necessarily how to code a function using the software constructs of RTL. After you know what the desired hardware function is, then code the RTL to implement that function. What you should do to answer your question is ask yourself what hardware am I trying to create, and will this for loop create it. I recommend an excellent book that covers a lot of coding techniques for various hardware functions in VHDL and Verilog. It is "HDL Chip Design. A practical guide for designing, synthesizing and simulating ASICs and FPGAs using VHDL or Verilog" by Douglas J. Smith. I consider this book a must have for front end design. It has many examples of good and bad code.
though synthesizable but it is not too friendly in terms of resources as well as synthesis time. If it is a small loop it may be ok, but if it is a big one..or loop inside loop then syntheis tool first have to unroll the whole logic and do the implementation..which may not always provide good quality of result both in terms of timing + area. Thats why "for" loop is preferred only for Testbench and not for RTL..but at the same time it is used for selective cases in RTL too.