Showing posts with label IR drop. Show all posts
Showing posts with label IR drop. Show all posts

IR drop driven placement


The objective here is to explore placement techniques which can lead to reduction in IR drop. One way to do this is to place high current cells towards the periphery in a peripheral i/o design. Simple way to implement this is to have a fixed dummy block at the center of the chip and attach fake nets from it to cell instances in a DEF file. A commercial placer can then be used to place this netlist. After placement, fake blocks and nets can be deleted. This can lead to IR drop reduction.