Showing posts with label Jitter. Show all posts
Showing posts with label Jitter. Show all posts

Clock Jitter


Clock jitter is the deviation from the ideal timing of clock transition events. Because such deviation can be detrimental to high-speed data transfer and can degrade performance, jitter must bekept to a minimum in a high-speed system.

High-speed signaling is very sensitive to jitter. As signals toggle faster and faster, tighter restrictions fall on the signal transmitter and receiver. In many high-speed data applications, the clock edge must fall within a tight margin of time to capture data correctly. The more jitter in a system, the more often the clock edge will fall outside the margin. The frequency of clock edge deviations from theacceptable margin translates to the system's bit error rate (BER).

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