Showing posts with label Latency. Show all posts
Showing posts with label Latency. Show all posts

Clock Latency & clock skew


Clock latency means, the number of clock pulses required by the ckt to give out the first output. Generally we will observe this in pipelined ckts.

Clock skew means the time difference between the arrival of clk edge at different FFs. This skew is due to different clock tree paths.