Showing posts with label Logic Density. Show all posts
Showing posts with label Logic Density. Show all posts

Logic Density


Find the resource elements consumed during design stage that is before RTL coding.Is it necessarily needed to draw the low level gate elements to calculate the logic gate consumption..I don't think designers go for detailed low level diagrams to calculate the resource utilisation. Then how to approximately find the resources used in design?
Ans: The main purpose of this exercise is generally to find the number of Flops (or the synchronous elements) in the logic. Even before RTL coding one can get some basic ideas about the flops by guessing state elements, number of registers for counters, retime blocks etc. Then based on the type of circuitry we try to guess how much combinatorial logic will be there between per flops (eg for pipeline design , it will be
less) thats again some percentage of sequential elements. At this stage we dont try to include buffers/inverters for load or different fanouts. etc. They can be all part of the combinatorial logic.

At last an approximate number can be inferred giving the number of gates (depending upon technology library) for the RTL module.