Showing posts with label Power Analysis. Show all posts
Showing posts with label Power Analysis. Show all posts

Interview Question on Power Analysis


Your task is to do power analysis for a circuit that sends out a one-clock-cycle pulse on the done signal once every 16 clock cycles(done is ’0’ for 15 clock cycles, then ’1’ for one cycle, then repeat with 15 cycles of ’0’ followed by a ’1’, etc). You have been asked to consider three different types of counters: 1. Binary counter, 2. Gray-code counter, and 3. One-hot counter. (The table below
shows the values from 0 to 15 for the different encoding schemes) What is the relative amount of power consumption for the different options?

Additional Info:
Your implementation technology is an FPGA where each cell has a programmable combinational circuit and a flip-flop. The combinational circuit has 4 inputs and 1 output. The capacitive load of the combinational circuit is twice that of the flip-flop.

1. You may neglect power associated with clocks.
2. You may assume that all counters:
(a) are implemented on the same fabrication process
(b) run at the same clock speed
(c) have negligible leakage and short-circuit currents

Encoding:
The columns below represent, Decimal Gray One-Hot Binary in order
0 0000 0000000000000001 0000
1 0001 0000000000000010 0001
2 0011 0000000000000100 0010
3 0010 0000000000001000 0011
4 0110 0000000000010000 0100
5 0111 0000000000100000 0101
6 0101 0000000001000000 0110
7 0100 0000000010000000 0111
8 1100 0000000100000000 1000
9 1101 0000001000000000 1001
10 1111 0000010000000000 1010
11 1110 0000100000000000 1011
12 1010 0001000000000000 1100
13 1011 0010000000000000 1101
14 1001 0100000000000000 1110
15 1000 1000000000000000 1111

This question is asked widely in interviews worldwide with varying levels of difficulty. Please start discussing.

Tip: Capacitance is dependent upon the number of signals, and whether a signal is combinational or a flop.