Question 2: There are two bus masters linked to a central arbiter by individual request (REQ#) and grant (GNT#) signals. Each master has its own REQ# and GNT# lines. Apart from this the arbiter also receives an input reset (RST#) signal.
Consider the following timing specification: Whenever the signal RST# is deasserted and in the next clock cycle REQ# is asserted, the GNT# signal is asserted after 3 clock cycles after the REQ# assertion and remains high for 7 clock cycles. Write an 'e' code snippet to check for the above specification. Add to your code an assertion to check that only one GNT# signal is asserted by the arbiter at an instant
Question 3: Write a verilog code to generate the clock waveform shown in the following figure. The fall and the rising transitions have 300 ps and 200 ps jitter respectively.