Showing posts with label System Level. Show all posts
Showing posts with label System Level. Show all posts

System Architect for micro-architecture performance analysis and optimization during functional simulation


System Architect is comprised of a set of powerful, on-demand SystemC-compliant functions and analysis tools that enable micro-architecture performance analysis and optimization during functional simulation. The analysis provides a wide range of valuable information showing how to improve performance and power utilization. Seamlessly linked with Summit's Vista IDE , System Architect enables effective and rapid analysis of system performance and architectural tradeoffs using C and SystemC.

The System Architect API function set can be instrumented into any functional code to track tokens of data, log states and attributes. Textual reports and visualization tools allow designers to analyze actual key performance metrics, such as bus contention, memory utilization, and SW instruction distribution - all during standard functional simulation. These metrics are critical for analyzing micro-architecture bottlenecks, bandwidth limitations, and power tradeoffs.
Key Features:

   * On-demand SystemC-compliant API functions
   * Advanced textual and graphical reports
   * Analysis of data throughput and communication latencies
   * Dynamic resource utilization analysis (such as memories and FIFO's)
   * Software task distribution and processor utilization reports
   * Hardware/Software tradeoff analysis

How System-Level Trade-Offs Drive Data Converter Decisions


For both analog-to"digital converters (ADC) and digital-to"analog converters (DAC), system-level specifications have a strong influence on several aspects of the converter's design, including conversion rate, resolution, power dissipation and silicon area. With a special emphasis on broadband wireless applications, this white paper reviews the design trade-offs ranging from the converter's sampling rate to the choice of single- or multiple-chip system partitioning. Understanding these choices enables chip architects and designers to optimize their systems in accordance with their particular constraints and the characteristics of the data converters.