Showing posts with label SystemC. Show all posts
Showing posts with label SystemC. Show all posts

SystemC AMS – A New Proposal For Mixed-Signal Verification


With increasing analog and mixed-signal content on systems-on-chip, design teams are looking for faster ways to run system-level simulations. They also need to incorporate mixed-signal functionality into system-level design and architectural exploration. Spice and Fast Spice are too slow for full-chip, top-level verification, and even languages like Verilog-AMS can pose a performance bottleneck. In this article by Richard Goering, he speaks about what SystemC AMS is about, refrerring to white papers on Linear signal flow (LSF), Electrical linear networks (ELN) and Timed data flow (TDF).

Fast, Easy, and Flexible Power for System Designers


Systems designers are having a difficult time developing power subsystems that supply all of their system's power needs due to varied and changing power requirements. A new type of power subsystem—the field-programmable power subsystem or FPPS—squarely addresses this issue by providing a flexible approach that costs no more than conventional switching power subsystems. This white paper discusses the advantages and benefits of field-programmable power subsystems and discusses the many ways they reduce system-design risks.

SystemC


SystemC provides hardware-oriented constructs within the context of C++ as a class library implemented in standard C++. Its use spans design and verification from concept to implementation in hardware and software. SystemC provides an interoperable modeling platform which enables the development and exchange of very fast system-level C++ models. It also provides a stable platform for development of system-level tools.

The Open SystemC Initiative (OSCI) is an independent not-for-profit organization composed of a broad range of companies, universities and individuals dedicated to supporting and advancing SystemC as an open source standard for system-level design.

The specific purposes of this organization include:
1. Building a rich system-level design language and open source implementation based on C++ class libraries, called "SystemC",
2. Encouraging availability and adoption of intellectual property (IP), tools and methodologies based on SystemC,
3. The mechanisms that enable the continued growth of the SystemC community,
4. Defining interoperability criteria for IP and tools based on SystemC, (5) delivering updates to the SystemC Language Reference Manual (LRM) and open source implementation, and
6. The SystemC language via the IEEE.

The open source proof-of-concept SystemC 2.1 library and the transaction-level modeling (TLM) library have been updated.
Access: SystemC

Success stories from ST Microelectronics, Intel, IBM, QualComm, Texas Instruments and Conexant which were given in session 22 of the 2004 Design Automation Conference and can be accessed at: DAC

One of the major benefits of SystemC is the ability to model at the transaction level (TLM), where the use of simple function calls in communication modeling brings gains in both coding productivity and simulation speed. The TLM standard is now here and is being adopted. The OSCI TLM interface standard extends the practical value of the SystemC class library by providing a standard modeling kit for the construction of TLM interfaces, thus reducing the work needed to construct new interfaces and increasing the opportunities for interopability. At the same time, the release of version 2.1 of the SystemC class library has added new features which extend the utility of SystemC for
transaction level modelling.

A SystemC specification of the AMBA bus is now available free of charge. The specification is a fully cycle-accurate representation of the AMBA AHB protocol including the AHB-lite protocol that is widely adopted for high-performance bus-matrix architectures. The AMBA specification is an established, open methodology that serves as a framework for SoC designs, effectively providing the interconnect that binds IP cores together. The specification has been downloaded by more than 12,000 design engineers and implemented in hundreds of ASIC designs. The AMBA AHB cycle-level modeling specification is available now for download from: AMBA

Synthesis of SystemC can be performed using the Agility Compiler from Celoxica. The compiler synthesizes SystemC directly to high-density FPGA and programmable SoC logic and generates RTL VHDL and Verilog for SoC design. SoC designers using SystemC can maintain the C level of design abstraction throughout the entire SystemC design process while taking advantage of simulation speeds that are orders of magnitude faster than RTL. Thus, whole systems can now be verified using the same test-bench at all stages of the design process.

Forte Design Systems offers a Cynthesizer, a synthesis tool that delivers an implementation path from SystemC to RTL, verification, and co-simulation. Cynthesizer accelerates RTL delivery for leading-edge integrated circuits and systems-on-chip by automatically generating optimized RTL code from a C++ / SystemC algorithmic description. It can also be used to explore architectural trade-offs, e.g. area and performance. Significant productivity and quality-of-results improvements are being realized. For additional information, access: ForteDS

CoWare, Inc. has partnered with Forte to provide the first integrated SystemC-based solution for electronic system-level (ESL) design to implementation. The tight integration of CoWare's SystemC-based ConvergenSC system-on-chip (SoC) design tools and Forte's Cynthesizer SystemC behavioral synthesis product unites system architecture, simulation, and synthesis in a first-of-its kind flow. Users can explore and validate a design's system architecture in CoWare's ConvergenSC, then synthesize to RTL using Forte's Cynthesizer, and verify the RTL in a system context with the same SystemC model.

CoWare has also integrated its SPW digital signal processing application design tool with the Cadence Virtuoso custom design platform enabling wireless product design teams to reduce schedule risk through an evolutionary change of their methodology. SPW reference models have been instrumental in the successful tapeout of thousands of wireless designs to-date. The new flow enables broader reuse of the reference models for the RF and analog designer's benefit. By using SPW reference models throughout different design domains, wireless design teams can dramatically increase design efficiency and reduce risk. Starting from the SPW frontend, users can select the parts of the system that are used as the reference or testbench, and mark them for export. SPW automatically creates an optimized simulation model with interfaces based on SystemC signals and data types. SPW was enhanced with technology from the CoWare ConvergenSC platform design tool. Cadence's Virtuoso platform leverages the same SystemC technology based on the Cadence/CoWare technology alliance, readily importing the newly created SPW model. RF designers do not need to be familiar with SPW to benefit from the new flow. For additional information, access: CoWare

CoWare provides its tools to universities via its university program UniversityProgram@CoWare.com). For U.S. universities, there is no charge for ConvergenSC and LISATek and up to 300 licenses of SPW can be obtained for an annual fee of $500. For European universities and non-profit research, CoWare participates in the EUROPRACTICE program.

In India, IIT Delhi and IIT Kharagpur use ConvergenSC and LISATek to support courses on system level modeling, system synthesis and architecture design space exploration.

Free SystemC On-line Tutorial
Access: SCOTT