Generally wire load models are used in ASIC design. These wire load models will contain statistical values which are used in pre-layout simulation of ASIC. Since we are extracting resistance(R), capacitance(C) values in back end after place and route(P&R) phase we need to perform pre-layout simulation before P&R.
A wire load model attempts to predict the capacitance and resistance of nets in the absence of placement and routing information. The estimated net capacitance and resistance are used for delay calculation. Technology library vendors supply statistical wire load models to support estimation of wire loads based on the number of fanout pins on a net. You can set wire load models manually or automatically.