Showing posts with label cadence. Show all posts
Showing posts with label cadence. Show all posts

Acceleration And Emulation – Why HW/SW Integration Needs Both


Acceleration, Emulation, and FPGA prototypes are most talked about these days and each has a distinctive role to play. In our earlier post we reflected on the Cadence rollout of Palladium XP, a verification computing platform that unifies acceleration capabilities from the Incisive Xtreme product line with Incisive Palladium emulation, incorporating some of the strongest capabilities from each platform.  You can read the press release here, but in his blog Richard Goering looks at the larger story behind the announcement. Why put acceleration and emulation in a single environment? What role does either play in hardware/software integration? And how do we define "acceleration" and "emulation," anyway?

Cadence Debuts Verification Computing Platform


Cadence Design Systems, Inc. has announced a fully integrated high-performance verification computing platform, called Palladium XP, that unifies simulation, acceleration and emulation into a single verification environment. Developed to support next-generation designs, the highly scalable Palladium XP verification computing platform lets design and verification teams bring up their hardware/ software environment faster and produce better quality embedded systems in a shorter time.

Cadence Palladium XP supports design configurations up to 2 billion gates, delivering performance up to 4MHz and supporting up to 512 users simultaneously. The platform also provides unique system-level solutions, including low-power analysis and metric-driven verification.

"Our system-integration challenges require us to improve our tools and methodologies continuously. Cadence has kept pace with our requirements and provided us with an excellent verification computing platform," said Narendra Konda, Director of Engineering, NVIDIA. "Cadence Palladium XP helps us design, verify and integrate the hardware and software components of our advanced graphics processing unit (GPU) better than ever to stay at the top of our game."

The Palladium XP verification computing platform provides developers a high-fidelity representation of their design so they can quickly and confidently locate and fix bugs, resulting in better-quality IP, subsystems, SOCs and system. Design teams can "hot swap" simulation with acceleration and emulation in a scalable verification environment as needed, which speeds the verification process and enables early access to testing embedded software and evaluating performance implications of different IP and/or system architectures.

"With the introduction of multicore IP platforms, ARM and our customers are facing new design requirements to integrate and run complex CPU sub-systems with software," said Dr. John Goodenough, Worldwide Director of Design Technology at ARM. "Like its predecessor, the Palladium XP verification computing platform will be a valuable validation tool for these advanced designs. Our initial trials have shown that the Palladium XP runs current ARM workloads out of the box, with the additional ability to trade off domain utilization for higher performance."

Availability:

The Palladium XP verification computing platform is available now worldwide. It is offered in two configurations, XL for design teams, and GXL for enterprise-class global teams.

MIPI & SoC Integration Lunch & Learn Seminar


Cadence Design Systems and Virage Logic would like to invite you to an interactive Lunch and Learn session that is designed to provide the latest information about MIPI standards, how to design-in an optimized MIPI solution, and how to develop an effective verification strategy for MIPI System-on-Chip (SoC) integration success!
 
Seating is limited - Register Now

Wednesday, April 21, 2010                    This is a Free Educational Event
Cadence Design Systems                      Registration: 10:00 am - 10:30 am
2655 Seely Avenue                                Seminar: 10:30 am - 1:00 pm
Building 10 Auditorium                            Lunch Will Be Served  
San Jose, CA  95134
(off Montague Expressway near 880)
 
Can't Make It?
Here's an Online Solution:
 
Cadence provides online self-guided Hands-On trials of Verification IP and tools for you to test drive at your desk - no downloads, no installation, and no licenses to manage.

47 CEOs for Cadence


[Via Deepchip]

I feel even that baiting a big name CEO from EDA background, from the list will not help. This is more about the basics. They need a thinker who understands Cadence's past values and what could be done to bolster the true strengths. This a point of debate so lets debate!

Bottom line *grin* [Make me the CEO]

For the rest of this story see:
http://www.deepchip.com/wiretap/081211.htm


Your take on the Cadence-Mentor hostile takeover bid


---------- Forwarded message ----------
From: <jcooley@zeroskew.com>
Date: Wed, Jun 18, 2008 at 6:02 PM
Subject: Your take on the Cadence-Mentor hostile takeover bid


Yesterday, Cadence publically announced it was doing a $1.6 B hostile takeover bid on Mentor Graphics.

0.) If you need to be anonymous, say "please make me anon" here.
1.) As an EDA USER would a Cadence controlled Mentor be a good thing or a bad thing for you? Why?
2.) As an EDA VENDOR what did you think of this move by Mike Fister?
3.) As EITHER, do you want this merger to happen? (CHOOSE YES or NO)


I'll publish your responses to these questions in the next ESNUG.

- John Cooley
DeepChip.com




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