Showing posts with label e-verification. Show all posts
Showing posts with label e-verification. Show all posts

e Verification language is alive and well


According to Mitch Weaver, corporate vice president for front-end verification at Cadence, the e verification language is not only still alive but is thriving and growing. In this pre-DVCon interview, he answers questions about Cadence and industry support for the e language and the Specman/e verification environment, as provided by Incisive Specman Elite and Incisive Enterprise Simulator XL.[Via: Industry Insights]

e-language using Random generation approach


Specman e-language powered by random generation concept. specman e-language is an HVL (High Level Verification Language) and an IEEE standard language used for constructing complex verification Environments. ‘e’ code written can never execute stand-alone without the Specman tool. The primary purpose of Specman e-language verification environment is to find more complex bugs for a given DUT (VHDL/Verilog) rather than using Test benches written in Verilog or VHDL. Test benches written using ‘e’ language run on Random approach using the built in pseudo random mechanism and as well executed using Constrained Random approach!