Some nonzero skews can become useful by creating safety margins to guard against delay variations (Moving the skews toward the center of the permissible ranges, creating safety margins against potential timing violations).
When we look for optimal design solutions, we need to look at the bigger picture:
What is the problem we're trying to solve in the first place? Is minimizing clock skew the primary goal of our design?
No, the primary goal of any design is to meet the chip's timing requirements. Since logic path delays also determine the timing of a chip, minimizing skew is just one approach to meeting the timing specifications. If we consider skew in the context of chip timing, we would find a larger, multidimensional space in which to search for solutions. Designers can consider skew--much like logic functions, gate sizes, and supply voltages--as a design variable. In that sense, what we're really trying to achieve is not just a good clock design, but rather a closure of timing or a more robust timing of the chip.
More detailed explanation @ (EE Times)