Behavioral simulation: Simulation of digital circuit described in HDLs like verilog or VHDL. We simulate the behavior described in these language based designs. This the second step.
Static timing analysis: This tells us "What is the longest delay in my circuit?" Timing analysis finds the critical path and its delay. Timing analysis does not find the input vectors that activate the critical path. Done after synthesis, this is the third step.
Gate-level simulation: Differences between functional simulation, timing analysis, and gate level simulation. In this type of simulation the delays after the post layout stage are back annotated to the design using SDF and simulated. This gives close to a real chip simulation performance. This is the final step.
Transistor-level or circuit-level simulation: Mainly for mixed mode(mixed signal) circuits. For mixed mode circuit we must verify complete design on transistor level. This is an intermediate step based on how the design is setup and the flow.
- Behavioral simulation can only tell you only if your design will not work.
- Pre-layout simulation estimates your design performance.
- Finding a critical path is difficult because you need to construct input vectors to exercise the right paths.
- Behavioral simulation and Static timing analysis is the most widely used form of simulation.
- Formal verification compares two different representations. It cannot prove your design will work.
- Switch-level simulation can check the behavior of circuits that may not always have nodes that are driven or that use logic that is not complementary.
- Transistor level simulation is used when you need to know the analog, rather than the digital, behavior of circuit voltages.
- Trade-off in accuracy against run time.