Showing posts with label unit delay simulation. Show all posts
Showing posts with label unit delay simulation. Show all posts

Unit delay simulation - an intermediate step in Gate level simulation!


This is an intermediate step during Gate level simulation!

Unit delay simulation operates on the assumption that all the elements in a circuit posses identical delays. This has an advantage that it can be setup early in the flow when the post layout netlist is ready but before the SDFs are not available which could be due to the fact that the design is not timing clean and is in the process of being timinh closed.

Primarily Unit delay sims help in ironing out any possible simulation synthesis mismatches due to delta delay issues and so widely used in the industry. But this kind of simulation should not be used to generate test stimuli. If done, this will give a false sense of security as the timing for the actual circuit will not resemble the results shown by the unit delay simulation. Another major disadvantage of unit delay simulation is that since the elements have non-zero delay, the design cannot be rank-ordered for simulation and hence unnecessary evaluation of elements several times in a same period can happen.

Unit delay simulation is very useful for FPGAs and CPLDs. Since these are fixed array circuits of rows and columns with identical elements that may be a NAND or NOR gate or a collection of resistors and transistors. Switching elements connected in this way usually have the same switching speed in which case unit delay sims become very meaningful. If the switching speeds are integral multiples of one another unit delay sims can still be effectively implemented.