# Workplace FSM design challenge - Interview Question

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You are part of the ""Chakra" design team, a combined smart-watch and goggles. A senior manager is coming for a design review in the afternoon. Your project leader has to go out to lunch with the manager, and has left you to design the last state machine in the system before the design review

The functional requirements of the state machine are given below, where “a” means that a is true (in VHDL: equal to ’1’) and “!a” means that a is false (in VHDL: not equal to ’1’): Functional requirements:
1. The inputs are: a, b, j, k, m, and n.
2. The outputs are: y and z.
3. The initial state is S0.
4. If (the current state is S0) and a, then in the current clock cycle assign j to y.
5. If (the current state is S0) and !a, then in the current clock cycle assign k to y.
6. If (the current state is S0) and b, then in the next clock cycle assign m to z.
7. If (the current state is S0) and !b, then in the next clock cycle assign n to z.
8. If (the current state is S0) and b, then the next state shall be S1.
9. If (the current state is S0) and !b, then the next state shall be S2.
10. If the current state is S1, then the next state shall be S2.
11. If the current state is S2, then the next state shall be S0.

1. You may choose y and z to be either registered or combinational. Both may be combinational, both registered, or one combinational and one registered. One of the optimization goals below is to minimize the number of registers.
2. Your design shall satisfy the functional requirements
3. Your goals, in order of decreasing importance are
(a) minimum number of clocked (i.e., real) states
(b) minimum number of edges
(c) minimum number of transient states
(d) minimum number of registers

Solution:

This design uses a synchronous process to handle the state transitions and a combinational process for output assignments based on the current state and inputs. The code is written to optimize for the specified goals, including minimizing the number of clocked states, edges, transient states, and registers.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Chakra_State_Machine is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
a : in STD_LOGIC;
b : in STD_LOGIC;
j : in STD_LOGIC;
k : in STD_LOGIC;
m : in STD_LOGIC;
n : in STD_LOGIC;
y : out STD_LOGIC;
z : out STD_LOGIC);
end Chakra_State_Machine;

architecture Behavioral of Chakra_State_Machine is
type state_type is (S0, S1, S2);
signal current_state, next_state : state_type := S0;
begin
process(clk, rst)
begin
if rst = '1' then
current_state <= S0;
elsif rising_edge(clk) then
current_state <= next_state;
end if;
end process;

process(current_state, a, b)
begin
case current_state is
when S0 =>
if a = '1' then
y <= j;
elsif a = '0' then
y <= k;
else
y <= '0'; -- Default value when no condition is met
end if;

if b = '1' then
next_state <= S1;
z <= m;
elsif b = '0' then
next_state <= S2;
z <= n;
else
next_state <= S0;
z <= '0'; -- Default value when no condition is met
end if;

when S1 =>
next_state <= S2;

when S2 =>
next_state <= S0;

when others =>
next_state <= S0;
end case;
end process;
end Behavioral;