Technology
What are Chiplets and how they Assemble Into the Most Advanced SoCs
If you are interested in the latest trends and innovations in the semiconductor industry, you may have heard of chiplet…
Interview Questions
Tutorials
X-propagation and methods to avoid X pitfalls
Image courtesy: Google What is X-propagation? What are the sources of X-Values? What is the Impact of X-propagation? Wh…
Timing Exceptions
Multi-Cycle Paths and False Paths in Static Timing Analysis
Here is a summary of this insightful EDN article Introduction : The article discusses the challenges and importance of …
Zero Delay Simulation
Zero delay simulation , Why and When
Zero-delay simulation is a technique that is widely used in digital design verification, especially for gate-level netl…
unit delay simulation
Unit delay simulation, Why and When
Unit delay simulation is a technique for modeling the behavior of digital circuits in a discrete time domain. It is bas…
Logic Design
Interview Questions - Logic Design - Beginner - October 2023
How many NAND gates are needed to implement a full adder? Hint: Use the Boolean expression for the sum and carry outpu…
Top10
Top 10 Interview Questions and their Winning answers
Image courtesy: Bing Here are the top 10 common interview questions and some tips on how to answer them: Tell me about …
Technology
Great Opportunity to Market yourself for free!
Attention Students who are graduating! Would you like to present your recent innovations: The Digital Electronics Blo…
Interview Questions
Functional Verification Interview Question
One day at the lunch table in the cafeteria, your manager says that she recently learned that X-SIM, the VHDL simulato…
Puzzles
Workplace FSM design challenge - Interview Question
You are part of the ""Chakra" design team, a combined smart-watch and goggles. A senior manager is comin…
VHDL
VHDL Online resources
VHDL Books There are dozens of great books talking about VHDL modeling, simulation and synthesis. Here are some of the…
Power Analysis
Interview Question on Power Analysis
Your task is to do power analysis for a circuit that sends out a one-clock-cycle pulse on the done signal once every 16…
Physical Design
Clock network design
In this blog post, we will discuss some of the challenges and techniques involved in designing a clock network for a ve…
SPICE
Clock skew variation estimation
Clock skew variation estimation is an important topic in the design and analysis of high-performance digital circuits. …
Physical Design
Impact of dummy fill on timing
How can you quantify the impact of dummy fill on post-layout timing? Dummy fill can be inserted into a layout using SO…
Timing
The effect of whitespace and aspect ratio on wirelength and timing
Whitespaces (empty space) are inserted in layouts in order to increase the routing resources of the chip. Have you ever…
Statistical Timing Analysis
Investigation on timing analysis inaccuracies
Timing analysis inaccuracies due to crosstalk, multiple gate input switching, supply voltage variation, temperature, ma…
Physical Design
Distributions in statistical timing
How do you observe and highlight the impact of assumptions on gate-length variability distributions (if any) on final d…
Wire Length Models
Effect of WLM and target frequency on performance
How do you quantify the effect of WireLength Models (WLM) and target frequency on the post-routing timing results?
Power Supplies
Dynamic power supply
Power gating adds enabling signals to a power supply network; dynamic power supply management adjusts supply voltage ac…