Showing posts with the label Interview Questions

Multi-Cycle and False Paths

Zero delay simulation

Unit delay simulation

Interview Questions - Logic Design - Beginner - October 2023

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Functional Verification Interview Question

Workplace FSM design challenge - Interview Question

System Verilog Interview Questions

Interview Question on Power Analysis

Clock network design

Clock skew variation estimation

Impact of dummy fill on timing

The effect of whitespace and aspect ratio on wirelength and timing

Investigation on timing analysis inaccuracies

Distributions in statistical timing

Effect of WLM and target frequency on performance

Dynamic power supply

Clock tree theory

Statistical clock tree design

Randomized algorithm/approximation scheme for statistical timing analysis

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