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Interview Questions articles
RTL Design
The hardest logic design interview questions are not about definitions. They describe a failure on a real chip, such as a FIFO that fails at speed, a register that flips on its own or a reset that will not release cleanly, and ask you to reason from symptom to cause to fix. Below are ten such questions, each with a model answer, the points a strong candidate covers and the follow-ups interviewers tend to ask. Anyone who has sat a semiconductor…
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Murugavel Ganesan
August 29, 2025
Verilog
To divide a 1 GHz clock down to an average of exactly 622.08 MHz with digital logic only, use a phase accumulator: add 1944 every input cycle, modulo 3125, and produce one output pulse each time the sum wraps. That works because 1000 / 622.08 reduces exactly to 3125 / 1944, so the output alternates between periods of one and two input cycles, the long-run average is exact, and every output edge stays within one input cycle of its ideal position.…
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Murugavel Ganesan
August 29, 2025
Top10
The PCIe and CXL questions that come up most in semiconductor interviews cover ten areas: how PCIe evolved to PAM4 and FLIT mode, the three CXL protocols, how CXL shares the PCIe physical layer, coherency, error handling, power states, signal integrity at 64 GT/s and above, the protocol stack, use cases, and link bring-up debug. Interviewers are rarely after a recited specification. They want to see that you can explain why each feature exists, …
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Murugavel Ganesan
March 26, 2025
Interview Questions
The average RPM for the whole trip is 48 RPM, not 50. The motor turns the same number of revolutions in each direction, but it spends longer on the slow reverse leg, so the average must be weighted by time. Divide the total revolutions by the total time and you get the harmonic mean of 60 and 40, which is 48 RPM. Key takeaways Average speed is always total quantity divided by total time, never the plain average of two speeds. When equal a…
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Murugavel Ganesan
January 03, 2025
Verification
IP and full chip verification interviews check whether you can prove a design correct before it becomes silicon. Expect questions on planning, SystemVerilog and UVM testbenches, constrained-random stimulus, coverage, assertions and formal, and on the system-level problems that only appear when every block is connected. The 50 questions below cover all of these, and each now has a short model answer. Verification is the backbone of chip desig…
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Murugavel Ganesan
January 03, 2025
Top 50
Design for Test (DFT) interviews test whether you understand how a chip is made testable after manufacture: scan insertion, fault models, ATPG, test compression, boundary scan, memory and logic BIST, and how coverage turns into shipped quality. The 50 questions below are the ones that come up most often, each with a short model answer you can build on. Interviewers rarely want definitions alone, so expect follow-ups on trade-offs, numbers and ho…
by
Murugavel Ganesan
January 03, 2025
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