- used to save power by masking the clock to the flops.
- used in clock switching circuits.
- Reduces routing burden and area to some extent.
- Ex: Suppose there are 8 D flops(DffL) with common load signal, we can replace all those loadable flops with simple D (Dff) flops and a clock gating circuit. This will reduce routing effort for the load signals to all flops. The area we are saving here is 8*(DffL/Dff). Of course we are adding clock gate area extra.
Disadvantages:
- There should not be any glitch on the gating signal, and the gating signal should transit only during the clock's inactive level.
- For DFT, the gating signal will be forced to a value so that the clock will be active during DFT testing.
- Introduces delay on the clock line.
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