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Assume a clock-gating scheme for turning off the clock in certain situations: 60% of the time, the main circuit has valid data the clock gating circuitry is 80% effective the clock gating circuitry has a capacitance equal to 15% of the main circuit the clock gating circuitry has an activity factor equal to 1.1 times that of the main circuit. How much power will be saved (as a percentage of the original power) by this clock gating scheme? …
Clock latency means, the number of clock pulses required by the ckt to give out the first output. Generally we will observe this in pipelined ckts. Clock skew means the time difference between the arrival of clk edge at different FFs. This skew is due to different clock tree paths.
Advantges: used to save power by masking the clock to the flops. used in clock switching circuits. Reduces routing burden and area to some extent. Ex: Suppose there are 8 D flops(DffL) with common load signal, we can replace all those loadable flops with simple D (Dff) flops and a clock gating circuit. This will reduce routing effort for the load signals to all flops. The area we are saving here is 8*(DffL/Dff). Of course we are adding clock gat…
Primarily design for low power depends on the characteristics design being accomplished. If it is a multi-million gate design we cannot implement any technique that is gate specific, it has to be a global technique. Multi-Vdd, variable Vdd and Multi-Vth seems to be a good global solution. Reducing the clock speed will result in low power consumption, but on the cost of performance. Using power headers and power footer transistors on logic gates …