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Showing posts with label Gated clocks. Show all posts
Showing posts with label Gated clocks. Show all posts

## Interview Question - Bangalore

Assume a clock-gating scheme for turning off the clock in certain situations:
• 60% of the time, the main circuit has valid data
• the clock gating circuitry is 80% effective
• the clock gating circuitry has a capacitance equal to 15% of the main circuit
• the clock gating circuitry has an activity factor equal to 1.1 times that of the main circuit.
How much power will be saved (as a percentage of the original power) by this clock gating scheme?

Solution: 15.5%
Want a full solution?

Difficulty: Medium

## Clock Latency & clock skew

Clock latency means, the number of clock pulses required by the ckt to give out the first output. Generally we will observe this in pipelined ckts.

Clock skew means the time difference between the arrival of clk edge at different FFs. This skew is due to different clock tree paths.
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1. used to save power by masking the clock to the flops.
2. used in clock switching circuits.
3. Reduces routing burden and area to some extent.
4. Ex: Suppose there are 8 D flops(DffL) with common load signal, we can replace all those loadable flops with simple D (Dff) flops and a clock gating circuit. This will reduce routing effort for the load signals to all flops. The area we are saving here is 8*(DffL/Dff). Of course we are adding clock gate area extra.

1. There should not be any glitch on the gating signal, and the gating signal should transit only during the clock's inactive level.
2. For DFT, the gating signal will be forced to a value so that the clock will be active during DFT testing.
3. Introduces delay on the clock line.

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## Low power design

Primarily design for low power depends on the characteristics design being accomplished. If it is a multi-million gate design we cannot implement any technique that is gate specific, it has to be a global technique.
1. Multi-Vdd, variable Vdd and Multi-Vth seems to be a good global solution.
2. Reducing the clock speed will result in low power consumption, but on the cost of performance.
3. Using power headers and power footer transistors on logic gates cuts down power.
4. You could separate the design in blocks, which can go in to sleep mode.
5. Another solutions is variable VDD and variable frequency (as Intel or AMD do).This means, you adapt VDD and frequency to the necessary performance.
6. Gated clocks and Logic Addressable clocks, dis adv - timing problems due to improper latching of signals, and difficult to test.
7. -ve edge triggered flops, (nor+inv) = 1.5 gates, +ve edge triggered flops, (and+inv) = 2.5 gates, so -ve has less gates, less glitching and hence low power.

Any more thoughts and ideas are welcome.