Setup and Hold times

The setup time is the time the data inputs must be valid before the clock/strobe signal.

• tSU(chip-pin)= tSU(FF) - Tdelay_clk_min(chip-pin to FF-pin) + Tdelay_data_max(chip-pin to FF-pin)

The hold time is the time the data must remain valid after the clock/strobe signal.

• tH(FF) = clk2Q + Tcomb+T(clk-skew), where T(clk-skew) = clk diff b/w source and destination flops. If source sees clk at X and destination flop sees clk at Y, T(clk-skew) = Y-X
• tH(chip-pin)= tH(FF) - Tdelay_clk_min(chip-pin to FF-pin) + Tdelay_data_max(chip-pin to FF-pin)

A zero setup time means that the time for the data to propagate within the component and load into the latch is less than the time for the clock to propagate and trigger the latch.

A zero hold time means either that the moment the clock is asserted, the latch no longer looks at its inputs, or that the clock path delay is shorter than the data path delay.

A negative setup or hold time means that there is an even larger difference in path delays, that even if the data is sent later than the clock (for setup time), it still arrives at the latch first.

Manufacturers avoid specifying negative values since this restricts later design and manufacturing decisions, but they often specify zero values since this simplifies usage in a system.