Intrinsic device delay: Time taken for the cell to change state due to a change on the input pins.
Interconnect delay: Delay due to wires. Dependent on layout. Smaller dimensions means more resistance. Making the wires "taller" leads to more capacitance.
• The total delay is the sum of the gate delay and the interconnect delay. Delay is mostly determined by the layout (placement) but varies with temperature, voltage and process.
• At above 0.5 micron interconnect delays are 20% of the path delay.
With present technologies it is from 40 to 60%. Thus delays are less predictable.
• Delays are even becoming a function of cross talk.
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