Types of Timing Verification

Dynamic timing:

1. The design is simulated in full timing mode.
2. Not all possibilities tested as it is dependent on the input test vectors.
3. Simulations in full timing mode are slow and require a lot of memory.
4. Best method to check asynchronous interfaces or interfaces between different timing domains.

Static timing:

1. The delays over all paths are added up.
2. All possibilities, including false paths, verified without the need for test vectors.
3. Much faster than simulations, hours as opposed to days.
4. Not good with asynchronous interfaces or interfaces between different timing domains.

Timing delays are determined by the layout but vary with temperature, voltage and process factors.

1. The ASIC vendor will supply factors based on their technology to allow verification under different environments. These factors are called generally called best and worst case military, industrial and commercial. The nominal value of the delay will be multiplied by a factor chosen by the designer to best represent the final operating conditions or the system requirements.
2. However, some vendors have their technology characterised for all the possible operating points.
3. Worst case military results in the longest delays and thus the most setup time violations.
4. Best case commercial results in the shortest delays and thus the most hold time violations.

Calculation of an Estimated Delay:

1. In synchronous design timing issues should be considered when choosing the algorithm. Avoid long paths before a register stage.
2. Synthesis is constraint driven. This means that the synthesis tool will generate the circuit using timing as a critical factor.
3. The libraries from the vendor will include the intrinsic delays of the cells.
4. The wire load model is a statistically based estimate (provided by the vendor for the target die size) of the load a certain fan out will result in. This load is then used to calculate the propagation delay.
5. Floorplanning is a method that allows information about the placement of a cell to be used in timing estimation. As most routing will be close to the ideal this is the dominant source of the timing delays.
6. Rather than trusting a wire load model (which are becoming less accurate as path delays start to dominate) floor planning can be used.
7. This can give very accurate timing information provided the floor plan drives the layout.
8. A floor plan will restrict the layout tool often resulting in a less efficient use of the silicon die. Also as it is a manual process human error can become a factor. Some vendors for this reason do not offer floor planning in their design flow.
9. Physical synthesis is a new synthesis strategy. The synthesis tool will place the cells and calculate estimated delays based on the minimum distance in the x-y plane.
10. If the synthesis fails then a new placement or new cells would be synthesised.
11. The tool will output the netlist and the placement file.

Wire Load Model

1. Statistical estimate of the load.
2. If the estimate is too conservative then high drive cells are used and more power is consumed. If the estimate is too optimistic then there will be widespread timing problems.
3. Main drawback is that no information about placement or routing is available.