Interview Question - Design Guidelines

While you are shopping you encounter your supervisor from last year. He's now forming a startup company. He's writing up the design guidelines that all of their projects will follow. He asks for your advice on some potential guidelines.

What is your response to each question? What is the justification for your answer? What are the trade-offs between the two options?

1. Should all projects use an asynchronous reset signal, or should all use a synchronous reset signal, or should each project choose its own technique?
2. Should all projects use Latches, or should all use Flip Flops, or should each project choose its own technique?
3. Should all chips have registers on the inputs and outputs or should chips have the inputs and outputs directly connected to combinational circuitry, or should each project choose its own technique? By "register" we mean either flip-flops or latches, based upon your answer to the previous question. If your answer is different for inputs and outputs, explain why.
4. Should all circuit modules on all chips have flip-flops on the inputs and outputs or should chips have the inputs and outputs directly connected to combinational circuitry, or should each project choose its own technique? By "register" we mean either flip-flops or latches, based upon your answer to the previous question. If your answer is different for inputs and outputs, explain why.
5. Should all projects use tri-state buffers, or should all projects use multiplexor's, or should each project choose its own technique?

Sol to 1:
Synchronous reset: Synchronous reset leads to more robust designs. With asynchronous reset, a flop is reset whenever the reset signal arrives. Due to wire delays, signals will arrive at different flops at different times. If an asynchronous reset occurs at about the time as a clock edge, some flops might be reset in one clock cycle and some in the next. This can lead to glitches and/or illegal values on internal state signals.

The tradeoff is that asynchronous reset is often easier to code in VHDL and requires less hardware to implement.

Sol to 2:
Flip flops lead to more robust designs than latches. Latches are level sensitive and act as wires when enabled. For a latch based design to work correctly, there cannot be any overlap in the time when a consecutive pair of latches are enabled. If this happens, the value on a signal will “leak” through the latch and arrive at the next set of latches one clock phase too early. Thus, latch based designs are more sensitive to the timing of clock signals. Another disadvantage of
latches is that some FPGAs and cell libraries do not support them. In comparison, D-type flip flops are (almost?) always supported.

The tradeoff is that latches are smaller and faster than flip flops. A common implementation
of a flip-flop is a pair of latches in a master/slave combination.

Sol to 3:
Putting flops on inputs and outputs will make the clock speed of the chip less dependent of the propagation delay between chips. Flops can also be used to isolate the internals of the chip from glitches and other anomolous behaviour that can occur on the boards.

The tradeoff is that flops consume area and will increase the latency through the
chip.

Sol to 4:
Each project should adopt a convention of either using flops on inputs of modules or outputs of modules. It is rarely necessary to put flops on both inputs and outputs of modules on the same chip. This is because the wire delay between modules is usually less than a clock period. Putting flops on either the inputs or outputs is advantageous because it provides a standard design convention that makes it easier to glue modules together without violating timing constraints. If modules were allowed to have combinational circuitry on both inputs and outputs, the maximum
clock speed of the design could not be determined until all of the modules were glued together.

The tradeoff is that flops add area and latency. Sometimes there will be two modules where the combinational circuitry on the outputs of one can be combined with the combinational circuitry on the inputs of the second without violating timing constraints. This discipline prevents that optimization.

Aside: Sometimes, to meet performance targets, in situations such as this, a project will remove or move the flops between modules and do “clock borrowing” to fit the maximum amount of circuitry into a clock period. This is a rather low-level optimization that happens late in the design cycle. It can cause big headaches for functional validation and equivalence verification, because the specifications for modules are no longer clean and the boundaries between modules on the lowlevel design might be different from the boundaries in the high-level design.

Sol to 5:
Multiplexors lead to more robust designs. Tri-state buffers rely on analog characteristics of devices to work correctly. Latches can work incorrectly in the presence of voltage fluctuations or fabrication process variations. Multiplexors work on a purely Boolean level and as such are less sensitive to changes in voltages or fabrication processes.

The tradeoff is that latches are smaller and faster than multiplexor's.