This question involves doing some of the design work for a circuit that implements Instruction P and Instruction Q using the components described below.
Instruction P : (i+j+k+l)*m
Instruction Q: a*b*((a*b)+(b*d)+e)
P's Frequency of occurrence is 75%
Q's Frequency of occurrence is 25%
Component Delays:
2 i/p Mult - 40 ns
2 i/p Add - 25 ns
Register - 5ns
Instruction P : (i+j+k+l)*m
Instruction Q: a*b*((a*b)+(b*d)+e)
P's Frequency of occurrence is 75%
Q's Frequency of occurrence is 25%
Component Delays:
2 i/p Mult - 40 ns
2 i/p Add - 25 ns
Register - 5ns
- There is a resource limitation of a maximum of 3 input ports i.e, you can assume other inputs to be internal signals in the expression. (There are no other resource limitations.)
- You must put registers on the inputs not the outputs.
- The environment will directly connect your outputs (its inputs) to registers. So no addition register is counted.
- Each input value (a, b, d, e, i, j, k, l, m) can be input only once — if you need to use a value in multiple clock cycles, you must store it in a register.
- What is the fastest execution time (for the mixture of Instruction P and Instruction Q given above) that you can achieve for this design, and what clock period do you need to achieve it?
- Find a minimal set of resources that will achieve the performance you calculated.
Sol to 1: Fastest execution time 140ns, clock period 70ns
Sol to 2: Registers 3, Adders 2, Multipliers 1
Sol to 2: Registers 3, Adders 2, Multipliers 1
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