- For each of the code fragments, answer whether the code is legal VHDL.
- If the code is legal VHDL, answer whether it is synthesizable.
- If the code is synthesizable:
- answer whether it represents good coding practices.
- answer whether the signal w or y is combinational, a latch, or a flip-flop.
- If the the code is not legal, is not synthesizable, or does not follow good coding practices, explain why.
- The signals are declared as follows:
- a, b, c, d, w : std logic
- m, y : unsigned(15 downto 0)
process (a, b) begin
if a = '1' then
w <= b;
end if;
end process;
process (a, c) begin
if a = '0' then
w <= c;
end if;
end process;
unsynth: single assignment rule — can't have multiple processes driving the same signal
process begin
wait until rising_edge(a);
w <= not w;
end process;
good: w=flop // or bad coding style, because state machine without reset
b <= a;
if b = '1' generate
w <= c;
end generate;
if b = '0' generate
w <= d;
end generate;
Answer:
illegal: dynamic test in generate
process begin
w <= '0';
wait until (a = '0');
p: loop
wait until rising_edge(b);
next p when (a = '1');
w <= c xor d;
end loop;
end process;
Answer:
unsynth: different wait conditions
process (m) begin
for i in 15 downto 0 loop
if 3 >= i then
y(i) <= '0';
else
y(i) <= m(i-3);
end if;
end loop;
end process;
Answer:
good: y = comb
process begin
wait until rising_edge(a);
if b = '1' then
wait until rising_edge(a);
w <= b;
else
w <= c;
end if;
end process;
Answer:
good: w=flop
Difficulty: Easy
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