- Give a VHDL code fragment to implement a standard D flip-flop.
- Give a VHDL code fragment to implement a flip-flop with a multiplexer on its input (assume two inputs: a and b).
- Give a VHDL code fragment to implement a flip-flop with a chip select line and an asynchronous reset.
process(clk)
begin
if rising_edge(clk) then
q <= d;
end if;
end process;
Sol 2:
process(clk)
begin
if rising_edge(clk) then
if (sel = '1')
q <= a;
else
q <= b;
end if;
end if;
end process;
Sol 3:
process(clk, reset)
begin
if (reset = '1') then
q <= '0';
elsif rising_edge(clk) then
if (cs_select = '1') then
q <= d;
end if;
end if;
end process;
Difficulty: Easy
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