Look at the following block. This is the most common building in any FPGA. It is called a Logic Element(LE) by Altera and Configurable Logic Element(CLB) by Xilinx. The structure may not be accurate but illustrates the idea behind it.
We estimate the number of FPGA cells required for a design by counting the number of flip-flops and primary inputs that are in the fanin of each flip-flop. Only flip-flops count, because combinational signals are collapsed into the circuity within an FPGA cell. The circuitry for any flip-flop signal with up to four source flip-flops can be implemented on a single FPGA cell. If a flip-flop signal is dependent upon five source flip-flops, then two FPGA cells are required.
This technique is generally an overestimate, because a single cell can drive several other cells (common sub expression elimination).
Coming to the Question...
Map the combinational circuits below onto generic FPGA cells. You could explain in words on how you could achieve this or send me an email.
Appreciate your comments.
Based on the solution received, i will post the answers here later!
Correction: Xilinx CLB is Configurable Logic Block. The drawing is representing not CLB but a Slice.
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