The semiconductor industry is struggling to maintain its momentum down the path of Moore’s Law, and it is becoming clear that in addition to scaling line widths and chip sizes downward, some form of 3D IC integration will be necessary to achieve the interconnection density, manufacturing yields and cost targets. By vertically stacking and interconnecting semiconductor layers (3D integration), as opposed to continuing to shrink line widths, chip designers have the potential to get around the limitations of geometric scaling; enable a significant increase in performance and reduction in power consumption through reduced signal paths; and achieve true cost reduction through the use of proven fabrication techniques that will increase yields.
The crucial processing technology elements for 3D IC integration include: 1) through silicon via (TSV) formation; 2) wafer thinning; and 3) scalable wafer-level bonding technologies with 3D interconnect for W2W (wafer-to-wafer) or D2W (die-to-wafer) fabrication processes. The semiconductor manufacturers who adopt the optimum combination of these technologies will be the ones who lead the industry to the next level of higher device performance and lower fabrication costs.
Even as device physicists continue to debate whether the physical limits of 2D scaling will be reached at the 22-nm node or somewhere beyond, the rest of the industry is recognizing the increasing practical and financial constraints being imposed by each new milestone on the technology roadmap.
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