EDA Tools - VN-Cover Emulator Coverage Analysis for HW Emulation

VN-Cover Emulator by TransEDA enables engineers to obtain coverage on their SoCs in a hardware-accelerated environment and reach a level of confidence similar to that achieved using VN-Cover with software simulators. Using VN-Cover Emulator speeds up the overall verification task by providing better visibility on what has been covered, what is left, and when to stop verification.

Key Features:

* Coverage for statement, branch, toggle and FSM state and arc
* Verilog, VHDL and mixed-language support
* Detailed code coverage reports and graphical display
* Automatic FSM extraction and analysis
* Support for Cadence Palladium and Cobalt, EVE Zebu, Mentor Graphics Celaro and Vstation, and Verisity Xtreme