VLSI/ASIC/VHDL Interview Questions

1. **For a combinational process in VHDL, the sensitivity list should contain all of the signals that are read in the process. Please give a detailed reason and an exception to this statement.**

   *Reason:* The sensitivity list in a combinational process specifies the signals that, when changed, should trigger the execution of the process. In VHDL, a combinational process should be sensitive to all the signals that are read within the process to ensure that the process is re-executed whenever any of these signals change. This helps maintain the integrity of the design and ensures that the outputs are updated correctly based on the latest input values.

   *Exception:* If the process uses variables instead of signals internally and doesn't directly read or write any signals, then those signals do not need to be included in the sensitivity list.

2. **For a combinational process, every signal that is assigned to must be assigned to in every branch of If-Then-Else statement and Case statement. Why?**

   Assigning a signal in every branch of an If-Then-Else or Case statement ensures that the signal gets a value for every possible combination of input conditions. If a signal is not assigned in one branch, there may be situations where the signal retains its previous value, leading to unintended behavior. This practice helps avoid latches and ensures that the output is well-defined for all possible input conditions.

3. **Each signal should be assigned to in only one process. Please give a detailed reason and an exception to this statement.**

   *Reason:* Assigning a signal in multiple processes can lead to contention and race conditions. It makes the behavior of the design unpredictable and may result in simulation mismatches and synthesis issues. Keeping a signal assignment within a single process helps maintain a clear and predictable flow of data.

   *Exception:* Signals declared in a package and used for inter-process communication may be assigned in different processes, but caution must be taken to synchronize access to these signals to avoid race conditions.

4. **Separate unrelated signals into different processes. Give at least two reasons!**

   - *Simultaneous Execution:* Unrelated signals should be separated into different processes to enable their simultaneous execution. VHDL processes execute concurrently, so unrelated logic can be executed in parallel, improving simulation speed.

   - *Readability and Maintainability:* Keeping unrelated signals in separate processes enhances code readability and maintainability. It makes it easier to understand and modify specific functionalities without affecting unrelated parts of the design.

5. **In a state-machine, illegal and unreachable states should transition to the reset state. Explain.**

   Transitioning illegal and unreachable states to the reset state ensures that the state machine remains in a known and well-defined state when unexpected conditions occur. It helps prevent the system from entering undefined states that could lead to unpredictable behavior or errors.

6. **If your state-machine has less than 16 states, use a one-hot encoding. Explain.**

   One-hot encoding uses a flip-flop for each state, with only one flip-flop being set (hot) at a time. In state machines with fewer than 16 states, one-hot encoding is more area-efficient compared to binary encoding. It simplifies the logic and reduces the number of gates needed for state transitions, making the design more streamlined.

7. **Include a reset signal in all clocked circuits. Explain.**

   Including a reset signal in clocked circuits allows for a controlled and predictable initialization of the system. It ensures that the system starts in a known state and behaves reliably during power-up or other exceptional conditions. Reset signals help in preventing metastability issues and ensure proper functioning after a reset event.

8. **For implicit state-machines, check for reset after every wait statement.**

   Implicit state machines often use wait statements for synchronization. Checking for reset after every wait statement ensures that the system responds to reset signals promptly. It helps in maintaining a responsive and predictable behavior, especially in designs where asynchronous events might affect the state machine.

9. **Connect reset to the important control signals in the design, such as the state signal. Do not reset every flip-flop. Explain.**

   Resetting only the essential control signals, like the state signal, allows for a more targeted and controlled reset operation. Resetting every flip-flop could lead to unnecessary initialization and could impact the functionality of the design. Resetting only the critical control signals ensures a minimal and well-defined reset behavior.

10. **Use synchronous, not asynchronous reset. Explain.**

    Synchronous reset ensures that the reset operation occurs only at a specific edge of the clock signal, providing a well-defined and predictable behavior. Asynchronous resets, on the other hand, can lead to metastability issues and are generally harder to control. Synchronous resets help in avoiding race conditions and maintain a more robust and reliable design.