Design for Test (DFT) interviews test whether you understand how a chip is made testable after manufacture: scan insertion, fault models, ATPG, test compression, boundary scan, memory and logic BIST, and how coverage turns into shipped quality. The 50 questions below are the ones that come up most often, each with a short model answer you can build on. Interviewers rarely want definitions alone, so expect follow-ups on trade-offs, numbers and how you debugged a real coverage or pattern problem.
.jpeg)
DFT means adding testability features to a chip design so that manufacturing defects can be found quickly and cheaply on the tester. It includes scan insertion, boundary scan, built-in self-test (BIST) and the patterns that exercise them. Good DFT improves quality and yield learning, and demand for engineers who can do it well keeps growing as devices get larger and more complex. Whether you are a new graduate or an experienced engineer, the questions below cover fundamentals, methodology and industry practice.
Key takeaways
- Scan turns a sequential design into something close to combinational logic for testing: shift a pattern in, capture one or two clocks, shift the response out.
- Know the fault models (stuck-at, transition, path delay, bridging, cell-aware) and which defects each one targets.
- Test coverage drives shipped quality. A worked example below shows how a small coverage change moves defect levels by a factor of ten.
- Compression, power-aware patterns and hierarchical DFT are what make test practical on large SoCs.
- Be ready to name the standards: IEEE 1149.1 (JTAG), IEEE 1500 (core wrappers) and IEEE 1687 (IJTAG).
Quick reference: DFT standards
| Standard | What it covers |
|---|---|
| IEEE 1149.1 | Test access port (TAP) and boundary scan, widely called JTAG |
| IEEE 1149.6 | Boundary scan for AC-coupled and differential links |
| IEEE 1500 | Test wrappers around embedded cores |
| IEEE 1687 | Access to embedded instruments through reconfigurable networks (IJTAG) |
| IEEE 1838 | Test access for stacked dies in 3D ICs |
A minimal scan chain in Verilog
Many interviews start with "draw a scan flop". The model below is a mux-D scan flip-flop and a four-flop chain with a small testbench that shifts a pattern in, captures functional data and shifts the response out. It was compiled and simulated with Icarus Verilog.
// Mux-D scan flip-flop: functional data D in mission mode, scan data SI in shift mode
module scan_dff (
input wire clk,
input wire se, // scan enable: 1 = shift, 0 = capture / mission mode
input wire d, // functional data
input wire si, // scan in (from previous flop in the chain)
output reg q // also drives scan out to the next flop
);
always @(posedge clk)
q <= se ? si : d;
endmodule
// Four scan flops stitched into one chain
module scan_chain4 (
input wire clk, se, scan_in,
input wire [3:0] d,
output wire [3:0] q,
output wire scan_out
);
scan_dff f0 (.clk(clk), .se(se), .d(d[0]), .si(scan_in), .q(q[0]));
scan_dff f1 (.clk(clk), .se(se), .d(d[1]), .si(q[0]), .q(q[1]));
scan_dff f2 (.clk(clk), .se(se), .d(d[2]), .si(q[1]), .q(q[2]));
scan_dff f3 (.clk(clk), .se(se), .d(d[3]), .si(q[2]), .q(q[3]));
assign scan_out = q[3];
endmodule
module tb;
reg clk = 0, se = 0, scan_in = 0;
reg [3:0] d = 4'b0000;
wire [3:0] q;
wire scan_out;
integer i;
reg [3:0] pattern = 4'b1011, unloaded;
scan_chain4 dut (.clk(clk), .se(se), .scan_in(scan_in), .d(d), .q(q), .scan_out(scan_out));
always #5 clk = ~clk;
initial begin
// shift in the pattern, last bit first so that bit 0 ends in f0
se = 1;
for (i = 3; i >= 0; i = i - 1) begin
scan_in = pattern[i];
@(posedge clk); #1;
end
$display("after shift-in q = %b (expect 1011)", q);
// one capture clock with functional data
se = 0; d = 4'b0110;
@(posedge clk); #1;
$display("after capture q = %b (expect 0110)", q);
// shift out the captured response
se = 1;
for (i = 3; i >= 0; i = i - 1) begin
unloaded[i] = scan_out;
@(posedge clk); #1;
end
$display("unloaded = %b (expect 0110)", unloaded);
$finish;
end
endmoduleNote that while one pattern is shifted out, the next is normally shifted in at the same time, which is why test time depends on the longest chain.
Scan, compression and ATPG (questions 1 to 11)
1. Can you explain the scan insertion steps?
Start from a DFT-clean netlist (run DRC for uncontrollable clocks, asynchronous resets, latches and combinational loops). Replace flops with scan flops, add scan enable and test mode control, stitch the flops into balanced chains per clock domain, insert lock-up latches where chains cross clock edges, add compression logic if used, then reorder chains after placement to save wiring. Finish with scan DRC, STA in shift and capture modes, and a simulation of the scan patterns.
2. What is test compression and how does it work?
Most bits in a scan pattern are don't-cares. A decompressor on chip expands a few tester channels into many short internal chains, and a compactor (usually XOR based) squeezes the many chain outputs back into a few channels. Tester data and test time both shrink, often by one to two orders of magnitude depending on the design and the tool.
3. Describe the process of Automatic Test Pattern Generation (ATPG).
The ATPG tool builds a test model from the netlist and library, applies test-mode constraints, and builds the fault list. For each fault it finds input values that activate the fault and propagate its effect to an observable flop or output (classic algorithms are the D-algorithm, PODEM and FAN). It then fault-simulates each pattern to drop every other fault the pattern also detects, and compacts patterns to keep the count low.
4. What are the common fault models in DFT?
Stuck-at (a node fixed at 0 or 1), transition delay (slow-to-rise or slow-to-fall), path delay (a specific path too slow), bridging (two nets shorted), IDDQ (abnormal quiescent current), and cell-aware faults that model defects inside a standard cell from its layout.
5. How do you ensure test coverage in your designs?
Fix DFT rule violations early, make clocks and resets controllable, add test points where coverage is low, run ATPG for each fault model, and review the remaining undetected faults by category (untestable, ATPG-aborted, not controlled, not observed). Coverage is tracked from early RTL testability checks through to signoff.
6. What is boundary scan and how is it implemented?
Boundary scan, defined in IEEE 1149.1, places a cell at each I/O pin and links the cells into a shift register controlled through the TAP. It lets a board tester drive and observe pins without physical probes, which finds opens and shorts on the board and in the package. Implementation adds the boundary cells, the TAP controller, an instruction register and a BSDL file that describes the device to test tools.
7. Explain Built-In Self-Test (BIST) and its advantages.
BIST puts a pattern generator and response checker on chip. Memory BIST runs March algorithms on SRAMs; logic BIST uses an LFSR to create pseudo-random patterns and a MISR to compress responses into a signature. Advantages: at-speed testing, little tester data, and the ability to test in the field, which automotive safety mechanisms rely on.
8. What are test points and when should they be used?
Control points force a hard-to-set node to a value, and observation points capture a hard-to-see node into a scan flop. Use them where testability analysis or ATPG shows random-pattern-resistant logic, deep logic cones or low coverage, and to raise logic BIST coverage.
9. How do you handle test data volume and compression?
Use compression, choose the chain count and ratio to fit tester channels and memory, merge patterns, target fault models in a sensible order (stuck-at first, then transition), and avoid needless pattern sets. Questions 24 and 30 come back to the same theme.
10. Describe the role of DFT in reducing time-to-market for a product.
Well-planned DFT gives working patterns on first silicon, fast bring-up through scan dumps and JTAG access, quicker diagnosis of yield problems, and shorter test time in production, all of which shorten the path from tape-out to volume.
11. What is the purpose of a scan chain in DFT?
A scan chain links flops into a shift register in test mode so that every flop can be loaded with a known value and read out. This makes internal state fully controllable and observable, which is what lets ATPG treat sequential logic almost as combinational logic.
Power, access and coverage (questions 12 to 22)
12. How do you handle power-aware testing in DFT?
Scan shift toggles far more flops than normal operation, which can cause IR drop, overheating and false failures. Remedies include lower shift frequency, low-power fill of don't-care bits, gating flop outputs during shift, staggering capture clocks across domains, and limiting switching activity in ATPG.
13. What is the role of a test access port (TAP)?
The TAP is the IEEE 1149.1 interface: TCK, TMS, TDI, TDO and an optional TRST. A 16-state controller steps through instruction and data register scans, giving access to boundary scan, device ID, BIST control and debug features with only four or five pins.
14. Explain the concept of fault coverage.
Fault coverage is the percentage of all modelled faults detected by the patterns. Many tools also report test coverage, which removes faults proven untestable from the denominator. Always say which one you are quoting.
15. What is the difference between structural and functional testing?
Structural testing checks that the circuit was built correctly, using fault models and scan patterns independent of what the chip does. Functional testing runs the chip in mission mode and checks behaviour. Structural tests give measurable coverage at lower cost; functional tests catch some system-level and speed problems structural tests miss.
16. How do you deal with false positives in test results?
A good die failing is usually caused by timing problems in test mode, power droop, X-states reaching the compactor, tester setup issues or wrong pattern constraints. Diagnose with failure logs, re-simulate the failing patterns with timing, check shift and capture STA, and use X-masking where needed.
17. What is the significance of test vectors in DFT?
Test vectors are the stimulus and expected response applied by the tester. Their quality sets coverage, and their count sets test time and tester memory, so they connect DFT work directly to quality and cost.
18. Describe the process of test pattern generation.
See question 3. In practice the flow is: read netlist and library, define clocks and constraints, run DRC, generate patterns per fault model, simulate them with timing, and hand over in a tester format such as STIL or WGL.
19. What are the challenges in DFT for mixed-signal designs?
Analog blocks have no standard fault model, so tests are often specification based (gain, offset, linearity). Challenges include isolating analog blocks with wrappers, using loop-back between DAC and ADC, keeping digital test noise out of sensitive circuits and controlling test time. IEEE 1149.4 addresses analog boundary scan but is not widely used.
20. How do you ensure the reliability of test results?
Run timing-annotated simulation of patterns, check STA in every test mode, correlate across testers and sites, monitor yield trends and repeat measurements on known good and known bad parts.
21. What is the importance of DFT in the semiconductor industry?
Every chip shipped must be tested, and test cost and escaped defects both cost money. DFT makes it possible to reach high coverage on billions of transistors in seconds of tester time, and gives the diagnosis data foundries and design teams use to improve yield.
22. Explain the concept of testability analysis.
Testability analysis measures how hard each node is to control and observe, for example with SCOAP scores, before running ATPG. It points to logic that needs test points or redesign.
Tools, IP and cost (questions 23 to 33)
23. What are the common tools used in DFT?
The main commercial suites are Siemens Tessent, Synopsys TestMAX (including DFTMAX and TetraMAX ATPG) and Cadence Modus. They cover scan insertion, compression, ATPG, BIST, diagnosis and IJTAG.
24. How do you handle test data volume in large designs?
Use high compression ratios, hierarchical DFT so cores are tested in parallel, logic BIST for part of the coverage and sharing of identical cores through broadcast. See also question 9.
25. What is the role of DFT in IP integration?
Each IP needs a defined test interface: scan chains, wrappers (often IEEE 1500 style), BIST controllers and test patterns that can be retargeted from the core boundary to chip pins. Integration fails when IP arrives without this.
26. Describe the process of fault simulation.
The simulator applies patterns to the good circuit and to copies with each fault injected, and marks a fault detected when an output differs. It is used to grade patterns, including functional ones, and to drop detected faults during ATPG.
27. What is the significance of DFT in reducing manufacturing costs?
Shorter test time, fewer tester channels, cheaper testers through BIST, and early removal of bad dies before packaging all lower cost. Better diagnosis also speeds yield ramps.
28. How do you ensure the security of test data?
Scan chains can expose secret keys and internal state. Protections include locking test access with authentication, scrambling or resetting secure flops on entry to test mode, disabling JTAG after production, and keeping test patterns under access control.
29. What are the key considerations in DFT for FPGA designs?
FPGA vendors provide the device test, so user designs mostly rely on boundary scan for board test, readback of configuration, on-chip logic analysers for debug and configuration memory checks (CRC and scrubbing) for reliability.
30. Explain the concept of test compression techniques.
Beyond the basic idea in question 2, techniques include linear decompressors driven by continuous flow (as in embedded deterministic test), broadcast scan, XOR and MISR compactors, X-masking and X-tolerant compaction.
31. What is the role of DFT in yield improvement?
Scan diagnosis maps failing patterns to likely defect locations, and statistical analysis across many failing dies points to systematic layout or process issues the foundry can fix.
32. How do you handle test escapes in DFT?
Analyse returned parts, find the defect, check whether a fault model would have detected it, then add targeted patterns (transition, cell-aware, small-delay), tighten limits or add stress tests.
33. What is the importance of DFT in the design verification process?
DFT logic must be verified like any other logic: check mission mode is unaffected, simulate test modes, and verify equivalence before and after insertion. Test patterns are also verified with timing simulation before tape-out.
Planning, SoC and analog (questions 34 to 41)
34. Describe the process of test plan development.
Define the quality target (for example DPPM), list the fault models, choose architecture (chains, compression, BIST, wrappers), budget test time and pins, plan power limits and agree the flow and schedule with design and product engineering.
35. What are the common challenges in DFT for SoC designs?
Many clock and power domains, very large flop counts, IP from many sources, limited test pins, high scan power, and test scheduling across cores.
36. How do you ensure the scalability of DFT solutions?
Use hierarchical, core-based DFT with reusable wrappers, standard access networks (IEEE 1687) and scripts that work across projects.
37. What is the role of DFT in reducing time-to-market?
See question 10. A frequent follow-up is how DFT helps silicon bring-up; the answer is scan dumps, memory BIST and JTAG debug access from the first day.
38. Explain the concept of test coverage metrics.
Common metrics are fault coverage, test coverage, ATPG effectiveness and pattern count. Quality is often expressed in DPPM.
Worked example. The Williams and Brown model estimates defect level as DL = 1 - Y^(1 - T), where Y is process yield and T is fault coverage. With Y = 0.90 and T = 0.99, DL is about 0.00105, roughly 1,050 DPPM. Raising coverage to 0.999 brings it to about 105 DPPM. These numbers are illustrative, but they show why the last fraction of a percent of coverage matters.
39. What are the key considerations in DFT for analog designs?
Choose specification-based tests, add access points and test buses, use built-in measurement such as loop-back and on-chip monitors, keep test time low and isolate analog blocks during digital scan.
40. How do you handle test data management?
Keep patterns, scripts and tester programs under version control, link pattern versions to netlist versions and record coverage and test time for each release.
41. What are the key considerations in DFT for digital designs?
Controllable clocks and resets, no unwanted latches or combinational loops, balanced chains, compression, at-speed testing with on-chip clock controllers, power limits and memory BIST.
Methodology and trends (questions 42 to 50)
42. How do you integrate DFT methodologies in the design flow?
Run testability checks on RTL, insert DFT during or after synthesis, include test modes in STA and power analysis, rerun ATPG after physical changes and include DFT in signoff.
43. What is the significance of fault grading in DFT?
Fault grading measures how many faults a set of patterns detects, for example grading functional patterns to see what extra coverage they give beyond ATPG.
44. How do you optimise DFT for low power consumption?
See question 12, and also: make sure DFT logic is off in mission mode, use clock gating that is test aware and plan for power domains being switched off during test.
45. Describe the process of test point insertion.
Run testability analysis or ATPG to find hard nodes, choose control and observation points within an area budget, insert them, check timing and rerun ATPG to confirm the gain.
46. What are the advantages of hierarchical DFT methodologies?
Smaller ATPG runs per core, test reuse for identical cores, parallel testing, earlier pattern generation before the full chip is ready and easier engineering changes.
47. How do you handle scan chain reordering?
After placement the tool reorders flops within each chain to shorten wiring, while keeping chains balanced, within clock domains and correctly connected through lock-up latches. Hold timing on the short scan paths must then be checked and fixed.
48. What is the role of DFT in achieving high test coverage?
Without scan and controllable test modes, sequential ATPG on a large design reaches only modest coverage. With full scan, compression and test points, high-90s percent stuck-at coverage is common.
49. How do you validate the effectiveness of DFT strategies?
Compare coverage and test time against the plan, correlate with silicon yield and defect returns, and review diagnosis results to see which defects were caught by which tests.
50. What are the future trends in DFT?
Testing of chiplets and 3D stacks (IEEE 1838, known good die), streaming scan over high-speed interfaces, silicon lifecycle management with in-field monitors, in-system test for automotive safety under ISO 26262, and greater use of machine learning in diagnosis and pattern optimisation.
How interviewers probe these topics
- They draw a small circuit and ask you to find a stuck-at pattern by hand.
- They ask for test time arithmetic, for example: 10,000 patterns, longest chain 500 flops, shift at 50 MHz gives about 0.1 seconds of shift time (an illustrative calculation).
- They ask what you did about a coverage gap, and expect you to name fault categories and fixes.
- They probe at-speed testing: launch-on-shift versus launch-on-capture, and on-chip clock controllers.
Common mistakes in answers
- Mixing up fault coverage and test coverage.
- Forgetting lock-up latches between clock domains and hold fixing after reordering.
- Claiming 100 percent coverage without mentioning untestable and redundant faults.
- Ignoring scan shift power.
FAQ
Which DFT topics matter most for freshers?
Scan flops and chains, stuck-at and transition faults, the basics of ATPG and the JTAG TAP. Related glossary entries: DFT, scan chain, ATPG, stuck-at fault and JTAG.
What do experienced DFT engineers get asked?
Compression architecture, hierarchical DFT, at-speed and power-aware patterns, silicon diagnosis and how they met a DPPM target.
Is memory BIST part of DFT?
Yes. Memories are tested with memory BIST and repaired with redundant rows and columns, and that work is usually owned by the DFT team.
Your comments will be moderated before it appears here.