Showing posts with label CDC. Show all posts
Showing posts with label CDC. Show all posts

Diagnosing clock domain crossing errors in FPGAs


Clock domain crossing (CDC) errors in FPGAs are elusive, and locating them often requires good detective work and smart design as well as an understanding of metastability and other physical behaviors. This white paper discusses the nature of CDC errors and presents a powerful solution that aids in their detection and removal.Note: By clicking on the above link, this paper will be emailed to your TechOnline log-in address by Mentor Graphics.

Clock-Domain Crossing Verification Module


This Mentor's Verification Academy module directly addresses CDC issues by introducing a set of steps for advancing an organization’s clock-domain crossing verification skills, infrastructure, and metrics for measuring success while identifying process areas requiring improvement. This Clock-Domain Crossing Verification Module contains 7 sessions total including 1 demo.