Showing posts with label Default Path. Show all posts
Showing posts with label Default Path. Show all posts

Default paths and False paths


The path in digital circuits which is not associated with a clock, is known as default path.

While considering and calculating the paths, we take into consideration the input point and the output point. Input points are usually clocks and input port. Output points are D input and output port.

A false path is a logic path in the design that exists but should not be analyzed for timing. For example, a path can exist between two multiplexed logic blocks that are never selected at the same time, so that path is not valid for timing analysis. Declaring a path to be false removes all timing constraints from the path.

Another example of a false path is a path between flip-flops belonging to two clock domains that are asynchronous with respect to each other.

e.g scan multiplexer.

Synthesis spends more time on optimizing the unwanted part of the logic when false path is not specified.

http://www.vlsichipdesign.com/static%20timing%20analysis.html