Showing posts with label False Path. Show all posts
Showing posts with label False Path. Show all posts

High level analysis of false paths


Sometimes the delay through a component is dependent upon the values on signals. This is because different paths in the circuit have different delays and some input values will prevent some paths from being exercised. Here are two simple examples:
  1. In a ripple-carry adder, if a carry out of the MSB is generated from the least significant bit, then it will take longer for the output to stabilize than if no carries generated at all.
  2. In a state machine using a one-hot state encoding, false paths might exist when more than one state bit is a '1'.
Because of these effects, static timing analysis might be overly conservative and predict a delay that is greater than you will experience in practice. The most accurate delay analysis requires looking at the actual data values that will occur in practice. Conversely, a timing simulation may not demonstrate the actual slowest behaviour of your circuit: if you don't ever generate a carry from LSB to MSB, then you'll never exercise the critical path in your adder.

Default paths and False paths


The path in digital circuits which is not associated with a clock, is known as default path.

While considering and calculating the paths, we take into consideration the input point and the output point. Input points are usually clocks and input port. Output points are D input and output port.

A false path is a logic path in the design that exists but should not be analyzed for timing. For example, a path can exist between two multiplexed logic blocks that are never selected at the same time, so that path is not valid for timing analysis. Declaring a path to be false removes all timing constraints from the path.

Another example of a false path is a path between flip-flops belonging to two clock domains that are asynchronous with respect to each other.

e.g scan multiplexer.

Synthesis spends more time on optimizing the unwanted part of the logic when false path is not specified.

http://www.vlsichipdesign.com/static%20timing%20analysis.html