Showing posts with label SOC. Show all posts
Showing posts with label SOC. Show all posts

MIPI & SoC Integration Lunch & Learn Seminar


Cadence Design Systems and Virage Logic would like to invite you to an interactive Lunch and Learn session that is designed to provide the latest information about MIPI standards, how to design-in an optimized MIPI solution, and how to develop an effective verification strategy for MIPI System-on-Chip (SoC) integration success!
 
Seating is limited - Register Now

Wednesday, April 21, 2010                    This is a Free Educational Event
Cadence Design Systems                      Registration: 10:00 am - 10:30 am
2655 Seely Avenue                                Seminar: 10:30 am - 1:00 pm
Building 10 Auditorium                            Lunch Will Be Served  
San Jose, CA  95134
(off Montague Expressway near 880)
 
Can't Make It?
Here's an Online Solution:
 
Cadence provides online self-guided Hands-On trials of Verification IP and tools for you to test drive at your desk - no downloads, no installation, and no licenses to manage.

Show Me the Next-Generation HDMI


The first part of this white paper explores the basic concepts behind HDMI, the markets it serves and its leadership role in multimedia interfaces. This is followed by a tutorial on the new capabilities of HDMI 1.4 and their role in providing a richer, more straightforward user experience. Next, we'll explore a series of user case scenarios that illustrate how the HEAC feature can simplify cabling requirements between digital home multimedia devices. The last portion of this paper discusses the architectural considerations and technical details involved with incorporating the Ethernet and Sony/Philips Digital Interconnect Format (S/PDIF) standards into the HDMI system-on-chips (SoCs) to support the HEAC feature.

Application Specific IP


One of the major barriers for Semiconductor IP commercialization is to provide evidence for an IP's quality. A common approach by IP vendors is to prove the quality of their IP in a test chip. Usually the Die contains the IP block separated from the System-on-a-Chip (SoC). It is, though, uncertain how the block will function in ASSP and ASIC products, potentially damaging its perceived commercial value. In Rosetta's methodology, the IP Core is a block within a subsystem, integrated to enable the subsystem functionality and targeted for a specific market and application. By analyzing the specific requirements of the market and application, and by providing an IP package targeted at those requirements, we solve and mitigate the IP quality

SOC interconnect Bus


SOC interconnect bus: These buses are used within a chip to interconnect an different IP cores to the surrounding interface and peripheral logic.

Some buses...

  1. Atlantic Interface, Avalon Bus Specification -- Altera corp.
  2. WISHBONE -- Opencores.org.
  3. AMBA, AHB (Advanced High-performance Bus) , APB (Advanced Peripheral Bus), ASB(Advanced System Bus) -- ARM.
  4. CoreConnect Bus -- IBM.
  5. Open Core Protocol 'OCP' -- Open Core Protocol International Partnership (OCP-IP)

Low power design


Primarily design for low power depends on the characteristics design being accomplished. If it is a multi-million gate design we cannot implement any technique that is gate specific, it has to be a global technique.
  1. Multi-Vdd, variable Vdd and Multi-Vth seems to be a good global solution.
  2. Reducing the clock speed will result in low power consumption, but on the cost of performance.
  3. Using power headers and power footer transistors on logic gates cuts down power.
  4. You could separate the design in blocks, which can go in to sleep mode.
  5. Another solutions is variable VDD and variable frequency (as Intel or AMD do).This means, you adapt VDD and frequency to the necessary performance.
  6. Gated clocks and Logic Addressable clocks, dis adv - timing problems due to improper latching of signals, and difficult to test.
  7. -ve edge triggered flops, (nor+inv) = 1.5 gates, +ve edge triggered flops, (and+inv) = 2.5 gates, so -ve has less gates, less glitching and hence low power.

Any more thoughts and ideas are welcome.

Application Specific Integrated Circuit ( ASIC )


An application-specific integrated circuit or ASIC comprises an integrated circuit (IC) with functionality customized for a particular use (equipment or project), rather than serving for general-purpose use.

For example, a chip designed solely to run a cash register is an ASIC. In contrast, a microprocessor is not application-specific, because users can adapt it to many purposes.

The initial ASICs used gate-array technology.

The British firm Ferranti produced perhaps the first gate-array, the ULA (Uncommitted Logic Array), around 1980. Customisation occurred by varying the metal interconnect mask. ULAs had complexities of up to a few thousand gates. Later versions became more generalized, with different base dies customised by both metal and polysilicon layers. Some base dies include RAM elements.

In the late 1980s, the availability of logic synthesis tools (such as Design Compiler) that could accept hardware description language descriptions using Verilog and VHDL and compile a high-level description into to an optimised gate level netlist brought "standard-cell" design into the fore-front. A standard-cell library consists of pre-characterized collections of gates (such as 2 input nor, 2 input nand, invertors, etc.) that the silicon compiler uses to translate the original source into a gate level netlist. This netlist is fed into a place and route tool to create a physical layout. Routing applications then place the pre-characterized cells in a matrix fashion, and then route the connections through the matrix. The final output of the "place & route" process comprises a data-base representing the various layers and polygons in GDS-II format that represent the different mask-layers of the actual chip.

Finally, designers can also take the "full-custom" route in implementing an ASIC. In this case, an individual description of each transistor occurs in building the circuit. A "full-custom" implementation may function five times faster than a "standard-cell" implementation. The "standard-cell" implementation can usually be implemented quite a bit quicker and with less risk of errors, than the "full-custom" choice.

As feature sizes have shrunk and design tools improved over the years, the maximum complexity (and hence functionality) has increased from 5000 gates to 20 million or more. Modern ASICs often include 32-bit processors and other large building-blocks. Many people refer to such an ASIC as a SoC - System on a Chip.

The use of intellectual property (IP) in ASICs has become a growing trend. Many ASIC houses have had standard cell libraries for years. However IP takes the reuse of designs to a new level. Designers of most complex digital ICs now utilise computer languages that describe electronics rather than code. Many organizations now sell tested functional blocks written in these languages. For example, one can purchase CPUs, ethernet or telephone interfaces.

For smaller designs and/or lower production volumes, ASICs have started to become a less attractive solution, as field-programmable gate arrays (FPGAs) grow larger, faster and more capable. Some SoCs consist of a microprocessor, various types of memory and a large FPGA.

So having said, this blog is dedicated to Digital Electronics, VLSI, ASICs, SOCs etc.