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PCI Express-based MicroTCA platforms are generating more and more interest. This paper describes how small and cost-effective MicroTCA platforms can be built utilizing PCI Express. Furthermore, architecture options for multiprocessor implementations are described, including both standalone systems and clusters.
With the dramatic increase in development costs for state-of-the-art process technologies, such as next-generation automotive electronic systems, specialization of traditional microcontrollers no longer makes business sense. This white paper discusses a process to develop an exact microcontroller for a specific application by implementing it into an Altera Cyclone IV FPGA for prototyping and volume production. Verification, software development, and field testing can be done immediately after design or even in parallel.
Since the introduction of the original USB standard in 1996, the USB interface has become one of the most successful connectivity standards. In today's highly connected world, USB connections are found in the computing, consumer, mobile, industrial and automotive segments. With the trend of increasing data storage requirements driven by applications, such as high-definition video, combined with the desire to move this data quickly between host, storage, and portable devices, it was only a matter of time before there was a need to make this well-known standard even faster. This heralds the third-generation of this ubiquitous standard—the arrival of SuperSpeed USB 3.0. This white paper provides a comparison between USB 3.0 and USB 2.0, highlighting the new capabilities and advancements that have been made with this next-generation technology.
Virtualization technology has been used in high-end servers for quite some time. The evolution of virtualization has brought with it the desire to reduce the software (S/W) overhead portion of virtualization, particularly for I/O devices. This paper will begin with an introduction to the general concepts of virtualization and I/O virtualization. It will then discuss how I/O virtualization is addressed within the PCI Express specification and the changes required to add I/O virtualization support to an existing PCI Express interface. Additional PCI Express topics covered include: Single-Root I/O Virtualization (SR-IOV), Function Level Reset (FLR), Alternative Routing ID (ARI) and Address Translation Services (ATS).
Organizations need to know how changing requirements in a complex system will affect development. An effective change management process can help you better identify how alterations will affect cost and schedule so you can keep them in control. Read this white paper to learn ways to keep schedules and costs in line.
With the increasing clock speeds and the decreasing feature sizes found in today's nanometer designs, at-speed testing is a requirement to achieve high quality test results. In addition, new advanced fault models are also available to improve defect detection and lower DPM rates. Advanced at-speed test capabilities and some new fault models are described in this paper.
DRAM (Dynamic Random Access Memory) is attractive to designers because it provides a broad range of performance and is used in a wide variety of memory system designs for computers and embedded systems. This DRAM memory primer provides an overview of DRAM concepts, presents potential future DRAM developments and offers an overview for memory design improvement through verification.
Protect Your FPGA Against Piracy: Cost-Effective Authentication Scheme Protects IP in SRAM-Based FPGA Designs
This application note describes FPGAs (field-programmable gate arrays) and how they can hold the key functions and the intellectual property (IP) of a system. It discusses ways to protect IP against piracy. SHA-1 challenge-and-response authentication is judged as the most secure methodology. This document presents a cost-effective authentication scheme that protects IP in SRAM-based FPGA designs. The DS28E01 and DS28CN01 1-Wire devices are featured.
Process variability is posing considerable challenge to the capability of lithography and manufacturing techniques, and thus impacts both performance and yield of advanced node chips. To ensure the manufacturability and performance of chips at 22nm, one approach the industry is considering is restrictive design&mash;limiting the type and placement of features used in designs. Gridding of critical layers significantly reduces the total physical design space available and makes restrictive design possible. This paper examines the basics of gridding, the requirements for restrictive gridded design, and the automated methods for accurate checking of Restrictive Design Rules (RDRs). Resolving the debug challenges associated with the implementation of checking restrictive design and grid rules is also discussed.
Electronics designs have become extremely complex and intricate, creating a need for software tools that support automation, maintain accuracy, and meet short design cycles. Re-using previously designed circuitry has long been an option for meeting these needs, but has never been easy to implement. Software providers have made attempts at providing this capability, but their solutions haven't always caught on. With new, more efficient options at hand, will customers see the value? Will they give it a try? This paperintroduces a methodology that can handle today's data-filled design content and still produce proper, reusable designs.
ESL design and verification is an emerging electronic design methodology that focuses on the higher abstraction level. The basic essence is to model the behavior of the entire system using a high-level language such as C, C++, SystemC or SystemC TLM-2.0. ESL is evolving into a set of methodologies that enable embedded system design, hardware verification, debugging through to the hardware and software implementation of custom SoC, and Architecture and Performance analysis as well. This paper discusses Electronic System Level (ESL) design and the methodologies and the tools associated with it.
Today's FPGAs are doubling in capacity every 2 years and have already surpassed the 5 million equivalent ASIC gate mark. With designs of this magnitude, the need for fast flows has never been greater. At the same time, designers are seeking rapid feedback on their ASIC or FPGA designs by implementing quick prototypes or initial designs on FPGA-based boards. These prototypes or designs allow designers to start development, verification and debug of the design—in the context of system software and hardware—and also to fine tune algorithms in the design architecture. Quick and intuitive debug iterations to incorporate fixes are of great value. The ability to perform design updates that don't completely uproot all parts of the design that have already been verified is also a bonus! Whether the goal is aggressive performance or to get a working initial design or prototype on the board as quickly as possible, this paper provides information on traditional and new techniques that accelerate design and debug iterations.
If you have ever designed a standard cell ASIC from scratch, you probably still have the scars to show for it. Designing a standard cell ASIC is not for the weak-hearted. A new generation of ASIC, (dubbed the NEW ASIC), is gaining momentum as an alternative to both standard cell ASIC and FPGA design which is explained in this paper. This new generation of ASIC combines the fast turnaround, low up-front development costs and simple design flow benefits that are normally associated with FPGAs, with the low unit power consumption and cost approaching that of a standard cell ASIC.
This paper, using an example design, demonstrates how to meet challenging performance, latency and bandwidth goals by using the DesignWare Interconnect Fabric for the ARM AMBA 3 AXI while minimizing the total area, power consumption and number of top-level wires. The paper also studies the design requirements and examines the optimization features of the DesignWare Interconnect Fabric used to meet the stringent timing requirements. Detailed technical analysis is provided for the selected architecture, pipelining mode, arbitration scheme and the slave visibility feature employed to reach timing closure for the links with demanding performance requirements. Final results are presented based on the hybrid architecture of the DesignWare Interconnect Fabric used to optimize the infrastructure resulting in a reduction in area, power and routing congestion.
For both analog-to"digital converters (ADC) and digital-to"analog converters (DAC), system-level specifications have a strong influence on several aspects of the converter's design, including conversion rate, resolution, power dissipation and silicon area. With a special emphasis on broadband wireless applications, this white paper reviews the design trade-offs ranging from the converter's sampling rate to the choice of single- or multiple-chip system partitioning. Understanding these choices enables chip architects and designers to optimize their systems in accordance with their particular constraints and the characteristics of the data converters.
Product quality and reliability are first-order design requirements for any product development. This document describes how quality and reliability can be dramatically improved with In-System Diagnostics. An overview is provided on common design verification and hardware validation challenges and how to overcome them with a single source solution.
Imagine being able to control electronics products at home and in the office, not with a direct touch but with the sweep of your hand. Advanced "touchless" human interface technology is now within the realm of practical implementation, even for products as commonplace as the alarm clock beside your bed. We all have experienced the frustration of locating the snooze and silence buttons on an incessantly beeping alarm clock at 6:00 a.m. What if you could extend your sleep just a bit longer by simply waving your hand or tapping a virtual button to shut off the alarm without fumbling to find the clock in the dark?
Since the year 2010 commercialization of the LTE technology is taking place. At the same time further enhancements of the LTE technology are worked on in order to meet ITU-Advanced requirements. This application note summarizes these necessary improvements known as LTE-Advanced.
The first part of this white paper explores the basic concepts behind HDMI, the markets it serves and its leadership role in multimedia interfaces. This is followed by a tutorial on the new capabilities of HDMI 1.4 and their role in providing a richer, more straightforward user experience. Next, we'll explore a series of user case scenarios that illustrate how the HEAC feature can simplify cabling requirements between digital home multimedia devices. The last portion of this paper discusses the architectural considerations and technical details involved with incorporating the Ethernet and Sony/Philips Digital Interconnect Format (S/PDIF) standards into the HDMI system-on-chips (SoCs) to support the HEAC feature.