Showing posts with label Technology Mapping. Show all posts
Showing posts with label Technology Mapping. Show all posts

Transistor level technology remapping


This is a process of combining several cells to form new library cells, and to optimize a transistor level netlist. This can be done algorithmically (e.g. pattern matching) or in an ad-hoc fashion. You can verify your area saving, timing improvement and power consumption reduction after this step.