Verilog Awareness

MG
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Differentiate between Inter assignment Delay and Inertial Delay ?

What are the different State machine Styles ? Which is better ? Why and when do we use one ove the other? Explain Disadv. and Adv.?

What is the difference between the following lines of code ?
  1. reg1<= #10 reg2 ;
  2. reg3 = # 10 reg 4 ;
What is value of Var1 after the following assignment ?
  1. reg Var1;
  2. initial begin
  3. Var1<= "-"
  4. end
What is the output of the below code?
  1. module quest_for_out();
  2. integer i;
  3. reg clk;
  4. initial begin
  5. clk = 0;
  6. #4 $finish;
  7. end
  8. always #1 clk = !clk;
  9. always @ (posedge clk)
  10. begin : FOR_OUT
  11. for (i=0; i < 8; i = i + 1) begin
  12. if (i == 5) begin
  13. disable FOR_OUT;
  14. end
  15. $display ( "Current i : %g" ,i);
  16. end
  17. end
  18. endmodule

What is the output of the below code?

  1. module quest_for_in();
  2. integer i;
  3. reg clk;
  4. initial begin
  5. clk = 0;
  6. #4 $finish;
  7. end
  8. always #1 clk = !clk;
  9. always @ (posedge clk)
  10. begin
  11. for (i=0; i < 8; i = i + 1) begin : FOR_IN
  12. if (i == 5) begin
  13. disable FOR_IN;
  14. end
  15. $display ( "Current i : %g" ,i);
  16. end
  17. end
  18. endmodule

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